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(parent: 1ccf6a5) | patch
Made small changes to fu/trap/main_stage to bring nmigen into line with
authorcolepoirier <colepoirier@gmail.com>
Fri, 5 Jun 2020 14:12:26 +0000 (07:12 -0700)
committercolepoirier <colepoirier@gmail.com>
Fri, 5 Jun 2020 14:13:25 +0000 (07:13 -0700)
commitb7b67db86e3199e6f48ce1c0ea798cf8b4dd09f3
treef48a75d3cdd4eee59c833a4372941854528fcf86tree
parent1ccf6a55ec5b0b99c166e0b047c325e8332701d0commit | diff
Made small changes to fu/trap/main_stage to bring nmigen into line with
microwatt VHDL
src/soc/fu/trap/main_stage.py diff | blob | history