add issuer verilog generator
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Jul 2020 19:44:18 +0000 (20:44 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Jul 2020 19:44:18 +0000 (20:44 +0100)
commitb7fa346690e88594c8fecccfe8be0f27e0b1265c
tree47e46042fb2e5bc978f1e940a46573f22d90e529
parent4b238fb9c21d072eb03d10fa51693cd2060876fe
add issuer verilog generator
src/soc/simple/issuer_verilog.py [new file with mode: 0644]