bleh. add XICS_ICS and XICS_ICP but the patch is

bleh. add XICS_ICS and XICS_ICP but the patch is
a little bigger than expected.
note that a bug ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits)
is also fixed here (whoops)

firstly, the XICS ICP and ICS need adding. but, they are
using make_wb_layout not wishbone.Interface.  therefore,
create a wishbone.Interface (sigh) and map the Signals across
one by one (just like with cvtuartbus)

secondly, the incoming IRQs are wired to GenericInterruptController
which is different from how Testissuer does it.

thirdly, eth_macs IRQ number is moved to 1 in order to match with
the Microwatt soc.vhdl

fourthly, uart_irq is set to 0

fifthly, UART16550 and EthMac needed to have their IRQLine
constructed *here* and passed in, otherwise the entire soc repo
becomes dependent on LambdaSoC just for that one import

sixthly, at the same time, DDRSoC has a uart_addr-0xc0002000 added
to match what soc.vhdl does

seventhly, eth0_cfg_addr is moved to 0xc000_c000 to get it out
of the way of XICS_ICP/ICS at 0xc000_4000 and 0xc000_5000

eigthly, xicx icp/ics are added at 0xc000_4000 and 0xc000_5000

totally broke the "one-purpose, one-commit" rule but not entirely
because after all this is "add XICS controller