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(parent: 86ebedd) | patch
End VL loop as soon as either src/dst step reaches VL
authorCesar Strauss <cestrauss@gmail.com>
Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)
commitb9e5fcccef1b8f74ef1ae271fa7d7e4d92bb65e3
treed1ab96dfb010345cdae74067e734311ac5d0f298tree
parent86ebedd0f5f65defdc2217a7c834c2f0c2ec108dcommit | diff
End VL loop as soon as either src/dst step reaches VL

Also, avoid incrementing dststep beyond VL-1
src/soc/decoder/isa/caller.py diff | blob | history