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(parent: c9d96f1) | patch
fix LDST PortInterface FSM interaction
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Aug 2020 15:38:47 +0000 (16:38 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 6 Aug 2020 15:38:50 +0000 (16:38 +0100)
commitba95c1a2d122f96f68f23aec2b9942c1b0d02e82
treeee6965544f11c78f8ac79914abc2afa0f36964edtree
parentc9d96f162b1bc4a48e95cd6a8ed25b82c11a95a4commit | diff
fix LDST PortInterface FSM interaction
when the WB Bus delayed "ack", the LDST PI FSM was not "listening" and
assumed that the operation had completed.  a bit of a rewrite was required
to get it to wait until LD/ST operations had actually fully completed
src/soc/experiment/pi2ls.py diff | blob | history
src/soc/experiment/pimem.py diff | blob | history