big (single-purpose) update: move width arg into pspec
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Jul 2019 16:07:16 +0000 (17:07 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Jul 2019 16:07:16 +0000 (17:07 +0100)
commitbaac5ec3d1e57c33baba0f4200a4a9af5efeceb5
treeddf2bd9529813d1330a7e5ec0bbee4e84e341cfb
parentefc955922d3d0f887a82b3011da619a02f3d93c2
big (single-purpose) update: move width arg into pspec
27 files changed:
src/ieee754/div_rem_sqrt_rsqrt/core.py
src/ieee754/fcvt/pipeline.py
src/ieee754/fpadd/add0.py
src/ieee754/fpadd/add1.py
src/ieee754/fpadd/addstages.py
src/ieee754/fpadd/align.py
src/ieee754/fpadd/pipeline.py
src/ieee754/fpadd/specialcases.py
src/ieee754/fpcommon/corrections.py
src/ieee754/fpcommon/denorm.py
src/ieee754/fpcommon/getop.py
src/ieee754/fpcommon/normtopack.py
src/ieee754/fpcommon/pack.py
src/ieee754/fpcommon/postcalc.py
src/ieee754/fpcommon/postnormalise.py
src/ieee754/fpcommon/roundz.py
src/ieee754/fpdiv/div0.py
src/ieee754/fpdiv/div1.py
src/ieee754/fpdiv/div2.py
src/ieee754/fpdiv/divstages.py
src/ieee754/fpdiv/pipeline.py
src/ieee754/fpdiv/specialcases.py
src/ieee754/fpmul/mul0.py
src/ieee754/fpmul/mul1.py
src/ieee754/fpmul/mulstages.py
src/ieee754/fpmul/pipeline.py
src/ieee754/fpmul/specialcases.py