add test of SRAM through wishbone bus
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Jun 2020 13:24:51 +0000 (14:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 26 Jun 2020 13:24:51 +0000 (14:24 +0100)
commitbb664403fa8d65dbaced112aae901f80399aba99
treef2d083f18c77fd7d090389218f5ee03b750c2787
parentb76bef1f8d6bb95a8a48875bc346199ac2d0443a
add test of SRAM through wishbone bus
src/soc/bus/test/test_minerva.py
src/soc/config/test/test_loadstore.py