First working version of the Flexlib + P&R flow for the ls180+SRAM.

First working version of the Flexlib + P&R flow for the ls180+SRAM.

Note: It is working in the sense that the flow complete, but is stills
      contains various errors that needs fixing.
        We discoupled from pinmux as core2chip have problems associating
      the pad instances names with the relevant core signals.
        We guessed a pad placement from pinmux, but it seems a bit odd
      to me...