set additional MSR bits according to v3.0B spec when trap occurs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 19:18:30 +0000 (20:18 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 22 Jul 2020 19:18:30 +0000 (20:18 +0100)
commitbd75d340d2ac47f9d02a0cff6547838f13f77a2f
tree7accf14c63acc8ea492aa252cc842bb056bddaf8
parent6e9aab358be8cd5f53494c035f0bc67dd7826b5d
set additional MSR bits according to v3.0B spec when trap occurs
src/soc/decoder/isa/caller.py