quick hack to SRAM test and to dcache to enable classic wishbone
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 2 May 2021 10:39:48 +0000 (11:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 2 May 2021 10:39:48 +0000 (11:39 +0100)
commitbe9e889729a3a0d9650dbb9d0b5931710d3bc10c
treef2c08f1cf42782ba5b1ee398ebc0749d81b7a20b
parent06c5bf3a6555eeb3e4ee87966bea3039a98aada3
quick hack to SRAM test and to dcache to enable classic wishbone
src/soc/bus/sram.py
src/soc/experiment/dcache.py