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(parent: d49f019) | patch
operating correctly, not directing MMU SPRs to SPR Pipeline,
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 2 Mar 2021 13:55:17 +0000 (13:55 +0000)
commitc0ff85b97953c6fd92b285dd6efd6fdc864ca3cf
treec8e95f374361869baa9bc8b192ebf2aa86c1b48btree
parentd49f0192f06d9df5ef5dbeb8fcefc7806409c729commit | diff
operating correctly, not directing MMU SPRs to SPR Pipeline,
failure with PC likely due to ISACaller not supporting SPR 720
src/soc/decoder/power_decoder2.py diff | blob | history
src/soc/fu/mmu/fsm.py diff | blob | history