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(parent: 3d1fbb5) | patch
blegh.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 16 Apr 2022 12:33:33 +0000 (13:33 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 16 Apr 2022 12:33:41 +0000 (13:33 +0100)
commitc18d53f534d25eb9728480b62e3fa0f0be13f96f
tree69e96de15e298be14731b0d52b0d37a68b81cf29tree
parent3d1fbb5790eaf4b74a96f16dc53369b458b2a727commit | diff
blegh.
* add in a new PRE_IDLE state into issue FSM (to allow pc_at_reset to
  get a word in edgeways)
* set nia to pc_at_reset on core_rst (not 0x0)
* add in a terrible hack where the STATE regfile entry for PC is
  shifted down by one.

absolutely no frickin idea why that is needed
Makefile diff | blob | history
src/soc/simple/core.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history