projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4acce7a) | patch
fix test_loadstore1.py with MSR=PR/DR
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 Dec 2021 14:22:17 +0000 (14:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 13 Dec 2021 14:22:17 +0000 (14:22 +0000)
commitc6cfd46e4c19dfa8c7b36ac39f6c7974df69ff2c
tree556cd8595a216c0d4af07bfbbc55b3d0808baa01tree
parent4acce7afb8839718216518468cd08a2999b18032commit | diff
fix test_loadstore1.py with MSR=PR/DR
for invalid test pr=1 but for others pr=0
src/soc/experiment/test/test_loadstore1.py diff | blob | history