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(parent: 9047bcb) | patch
repeated copies of read/write addr/sel to Cache SRAMs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 6 Dec 2021 16:01:13 +0000 (16:01 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 6 Dec 2021 16:01:13 +0000 (16:01 +0000)
commitcadcc6b7538df06ce6fb4614ba01152b700dd0d8
treedf03c5227856e225209e02ef90f934e183832f0ftree
parent9047bcb369ec804733bb1c595a2e203dc0e22588commit | diff
repeated copies of read/write addr/sel to Cache SRAMs
moved rd/wr addr/sel outside of loops, only creates one MUX set now
src/soc/experiment/dcache.py diff | blob | history
src/soc/experiment/icache.py diff | blob | history