alternative uart wishbone mapping which just takes 8-bit data and
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 15:57:58 +0000 (15:57 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 15:57:58 +0000 (15:57 +0000)
commitccdecf82a4cf4e3bfa35d25a10f8ed47958db8a8
tree2c26869a3e4645be792d1ba69becadb1a1ca742b
parent6d88cc5ca3b72929942a6cc3194521ae36b9eaaa
alternative uart wishbone mapping which just takes 8-bit data and
drops it onto 32-bit bus
src/ls2.py