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(parent: 61440c9) | patch
reorg of SO handling related to CR0
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 26 Aug 2020 17:59:47 +0000 (18:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Aug 2020 12:23:09 +0000 (13:23 +0100)
commitcd088b785ee6e4a9fd9e5c1b87c63a13e9e7386b
treeef3e8bb65dda225fcc62f02734e9701c6a8d7a77tree
parent61440c972436f418a0c115ac75153bce2bc50cb3commit | diff
reorg of SO handling related to CR0
because CR0 needs XER SO, logical pipe needs to read but not write SO
this means quite a substantial but relatively straightforward change
in the pipe_data for logical and ALU
src/soc/fu/alu/output_stage.py diff | blob | history
src/soc/fu/common_input_stage.py diff | blob | history
src/soc/fu/common_output_stage.py diff | blob | history
src/soc/fu/logical/main_stage.py diff | blob | history
src/soc/fu/logical/output_stage.py diff | blob | history
src/soc/fu/logical/pipe_data.py diff | blob | history
src/soc/fu/logical/test/test_pipe_caller.py diff | blob | history
src/soc/fu/test/common.py diff | blob | history