add bare wishbone option to TestIssuer, sort out ports
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Jul 2020 17:36:51 +0000 (18:36 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 2 Jul 2020 17:36:51 +0000 (18:36 +0100)
commitced643bf2009c34f948631ad8ac8763582393fdb
tree464058fbb38627afe60698710b105527f4828e7d
parentbecaa04fcfa10fb47a276da567786a1bc8224d85
add bare wishbone option to TestIssuer, sort out ports
src/soc/config/ifetch.py
src/soc/config/loadstore.py
src/soc/experiment/l0_cache.py
src/soc/experiment/pimem.py
src/soc/minerva/units/fetch.py
src/soc/minerva/units/loadstore.py
src/soc/simple/core.py
src/soc/simple/issuer.py