rename design of experiments10 to match ls180 chip pads
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 9 Apr 2021 12:05:11 +0000 (12:05 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 9 Apr 2021 12:05:11 +0000 (12:05 +0000)
commitcee93b0eff5511bf1a2da2692a902c199f5e41c1
tree1624fb4c0373b45cae41406d4a811d94c5f5cedd
parentacf9a74a04e8866aae0a738b02343ae772171b5e
rename design of experiments10 to match ls180 chip pads
experiments10_verilog/add.py
experiments10_verilog/coriolis2/settings.py
experiments10_verilog/doDesign.py
experiments9/Makefile
experiments9/build_full.sh