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(parent: 093ddeb) | patch
complete first translation pass of dmi_dtm_xilinx.vhdl into nmigen,
authorCole Poirier <colepoirier@gmail.com>
Wed, 16 Sep 2020 22:34:13 +0000 (15:34 -0700)
committerCole Poirier <colepoirier@gmail.com>
Wed, 16 Sep 2020 22:36:37 +0000 (15:36 -0700)
commitd050717ae4063eb3b8f61d71a949d0a1d5a70e71
tree4b969de7721ea1eee1b6d549aacf9a5419b092aatree
parent093ddebb6ba44f3edd291d699d775c6821b8d620commit | diff
complete first translation pass of dmi_dtm_xilinx.vhdl into nmigen,
different sync domains indicated as 'sync = m.d.[SYS|JTAG]_sync', left
some parts undone, didn't rearrange or clean up so Luke can easily
compare with original
src/soc/experiment/dmi_dtm_xilinx.py diff | blob | history