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(parent: 2b8f22c) | patch
only add clock-settings on ECP5 due to special SPI clock handling
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 6 Apr 2022 11:29:03 +0000 (12:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 6 Apr 2022 11:29:03 +0000 (12:29 +0100)
commitd1182f58945784de533ba81d4d4650cc5ec48dc0
tree04607fd867f6902d69fb535ce8af28fab3598f44tree
parent2b8f22c9caefd4238b26c1c9cfcfecc4372df262commit | diff
only add clock-settings on ECP5 due to special SPI clock handling
(Tercel QSPI)
src/soc/bus/tercel.py diff | blob | history