Demonstrates adding extra debug signals traces to the dump file
authorCesar Strauss <cestrauss@gmail.com>
Fri, 14 Aug 2020 11:06:49 +0000 (08:06 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sat, 15 Aug 2020 09:27:26 +0000 (06:27 -0300)
commitd3a72bb0688cf343dddc069ef50ba60b9736e8d9
tree5e961953ec3aea9240c8beb2cfcfcfca0e3d2f81
parentde64658d0a482f1d6df3c84b4087864ff65ccfef
Demonstrates adding extra debug signals traces to the dump file

At simulation time, you can declare a new signal, and use it inside
the test case, as any other signal. By including it in the "traces"
parameter of Simulator.write_vcd, it is included in the trace dump file.

Useful for adding "printf" style debugging for GTKWave.
src/soc/experiment/alu_fsm.py