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amd: Swap from nir_opt_shrink_load() to nir_opt_shrink_vectors().
authorEric Anholt <eric@anholt.net>
Thu, 23 Jul 2020 05:00:57 +0000 (22:00 -0700)
committerMarge Bot <eric+marge@anholt.net>
Mon, 3 Aug 2020 21:26:45 +0000 (21:26 +0000)
commitd8c2f896dba8b5e89f054dc9f6bffd27e3aceb25
tree1ff64a133f9c5aa592fec1b06d099cda10d3c827tree
parent023e6669cc1d7d321e0bd5b5293422cd73b3d658commit | diff
amd: Swap from nir_opt_shrink_load() to nir_opt_shrink_vectors().

This should do much more trimming than shrink_load, and is a win on i965's
vec4 and nir-to-tgsi.  For scalar backends like this that don't need ALU
shrinking, it still gets more load intrinsics covered.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6050>
src/amd/compiler/aco_instruction_selection_setup.cpp diff | blob | history
src/amd/vulkan/radv_shader.c diff | blob | history