add bus.err to list of default Wishbone signals in Tercel
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 19:43:10 +0000 (20:43 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 29 Mar 2022 19:43:10 +0000 (20:43 +0100)
commite71dc3c11a1085aa609833a4a3c2eecd2f18876e
tree0ffe13d1c946a7810219ca856d087e203e72b3a1
parentd1077d10e6391cbef04053ec255dd81b123aacb9
add bus.err to list of default Wishbone signals in Tercel
src/soc/bus/tercel.py