projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 918e1e8) | patch
thanks to daveshah, added simulation of dram
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 Aug 2020 23:20:00 +0000 (00:20 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 Aug 2020 23:20:07 +0000 (00:20 +0100)
commite9b34ea6f549ad990ab10d51a2886d26131c9442
treef86baa7cd5d8e99165bb34937ea02a4ea108efa1tree
parent918e1e838b3769ca14674865a32b9626a76c4471commit | diff
thanks to daveshah, added simulation of dram
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/84

this allows to track down a bug in the DDR3 memory test which is also
occurring in the FPGA version
src/soc/litex/florent/sim.py diff | blob | history