projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b450822) | patch
Implement a 1W/1R register file, XOR style
authorCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 22:27:58 +0000 (19:27 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 22:41:06 +0000 (19:41 -0300)
commitebd50443924d611f6492fb065ff7efd70f3c830a
tree8aa6ab7665b3006a492e9cb16d8ab4a7c170571ctree
parentb450822854a1c53d6909201989978e9ab40ede39commit | diff
Implement a 1W/1R register file, XOR style

Test case seems to be working.
Total 6x 1RW SRAMs were used, but no DFF RAM was needed.
Still needs a bypass for a transparent read option.
src/soc/regfile/sram_wrapper.py diff | blob | history