find semi-suitable width for spr0, add missing int dmi signals
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 5 Aug 2020 15:22:08 +0000 (15:22 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 5 Aug 2020 15:22:08 +0000 (15:22 +0000)
commitf12666dee5a09b4677632f5110d311b9e2ee0da9
treeec3cf65188174dc481204ecf7b0096f36bc88e40
parent0a54b783281715f4e972052899ef779ea86e904f
find semi-suitable width for spr0, add missing int dmi signals
experiments9/doDesign.py