projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 386b44d) | patch
whoops, a Simulation bug, dcache bus ack Signal needed to be
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 16 Dec 2021 17:07:58 +0000 (17:07 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 16 Dec 2021 17:07:58 +0000 (17:07 +0000)
commitf23716a9508b6696b6633083f9bb2c4353613c30
tree1a43ad94219335498d000e89a2162648cf7c871atree
parent386b44d4d41c8fefa0d03c80728fed2271da1638commit | diff
whoops, a Simulation bug, dcache bus ack Signal needed to be
copied into a separate combinatorial Signal
src/soc/experiment/dcache.py diff | blob | history