check cr0, ov and ca ok signals in ALU main_stage proof
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 27 May 2020 15:27:51 +0000 (16:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 27 May 2020 15:27:51 +0000 (16:27 +0100)
commitf2a184d68c12cc7243733c9cd87d20c074bb4c13
treef66aaed848a1d8ec2f6846b576c8dcd72d8437fb
parent32602780575dedfd322945760769201f0565cfe2
check cr0, ov and ca ok signals in ALU main_stage proof
src/soc/fu/alu/formal/proof_main_stage.py