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(parent: 1ad1e95) | patch
* add uart_pins to UART16550 peripheral so they get connected
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 16 Feb 2022 01:23:13 +0000 (01:23 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 16 Feb 2022 01:23:13 +0000 (01:23 +0000)
commitf2a19f9980138744d2eabe5581bd4d0238193719
treeba0f01146abdefa28d0e5004e52565247bd7f37dtree
parent1ad1e951155df66d277fa0b031959b6a01e77e4ecommit | diff
* add uart_pins to UART16550 peripheral so they get connected
* add yosys -abc9 option
* correct path to external_core_top.v
src/ls2.py diff | blob | history