projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 103d930) | patch
add exact same number - and name - bitvector ports to regfiles
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 11 Nov 2021 14:56:09 +0000 (14:56 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 11 Nov 2021 14:56:09 +0000 (14:56 +0000)
commitf3e4fdbdcef1700d595be868ec5a1cf8e2b1ce03
tree6c86a255f62b2c593f30300272f3d51a7d3e3b59tree
parent103d9306983e8782c930590fe58af2fc960ee216commit | diff
add exact same number - and name - bitvector ports to regfiles
for hazard purposes, easier to just have the exact same names
g
src/soc/regfile/regfiles.py diff | blob | history