projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ab38260) | patch
rename nia to cia in MMU input record and mmu FSM
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 14:24:20 +0000 (14:24 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Dec 2021 14:24:30 +0000 (14:24 +0000)
commitf57f94eedd990c5a52b7a53fce3dfedd7eb75348
tree15e1060c1fb097e1965690e0a852f5d2f4c3a05ftree
parentab38260fedb13b7b83cf2dbec6aa2ce44e8e3e88commit | diff
rename nia to cia in MMU input record and mmu FSM
this gets the PC passed over when an instruction fault occurs in
MSR.IR=True mode.

previous tests were only working because the instructions started at 0x0000
and a full cache line was read by I-Cache.  tests greater than a cache
line would have failed
src/soc/experiment/mmu.py diff | blob | history
src/soc/fu/mmu/fsm.py diff | blob | history
src/soc/fu/mmu/mmu_input_record.py diff | blob | history
src/soc/simple/test/test_issuer_mmu_ifetch.py diff | blob | history