add first cut of verilator simulation, over from microwatt
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 11:33:20 +0000 (11:33 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 14 Feb 2022 11:33:20 +0000 (11:33 +0000)
commitf5a155944859c68d6bd75309568a92cb4ca35329
tree06dc442f7e66a89e13cff5d5b32ab6f94f8a237d
parent2c35e5716c5239d0bce4bee08733029e451c1d08
add first cut of verilator simulation, over from microwatt
Makefile [new file with mode: 0644]
src/ls2.py
verilator/microwatt-verilator.cpp [new file with mode: 0644]
verilator/uart-verilator.c [new file with mode: 0644]
verilator/uart-verilator.h [new file with mode: 0644]