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(parent: a3fa9e2) | patch
First attempt at implementing block access rd and wr regfile port onto
authorcolepoirier <colepoirier@gmail.com>
Tue, 26 May 2020 01:04:37 +0000 (18:04 -0700)
committercolepoirier <colepoirier@gmail.com>
Tue, 26 May 2020 01:04:37 +0000 (18:04 -0700)
commitf690846a710a75ea8ed809a7b7a4351236210fc9
tree864c20f900202449d221e6ca9cd841f9296af9f3tree
parenta3fa9e226b53ae792650b7d50a29cb2b86bcf792commit | diff
First attempt at implementing block access rd and wr regfile port onto
an array-based regfile
src/soc/regfile/virtual_port.py [new file with mode: 0644] blob