experiment adding 3x extra SRAMs back in but still @ 32-bit WB
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 16:51:30 +0000 (16:51 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 16:51:30 +0000 (16:51 +0000)
commitf6af3ecf82e20b6cb0ba130fb5fd9cf5c47b82f9
treed346cb8f38937d92d309956ab0402acd281f4721
parentbb90898302b17a915b1bdedd8e83e5f50f033adb
experiment adding 3x extra SRAMs back in but still @ 32-bit WB
experiments9/non_generated/full_core_ls180.il