experimentation to get experiment10_verilog work with FreePDK
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 16:44:51 +0000 (16:44 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 16:44:51 +0000 (16:44 +0000)
commitf717bc2ba64501d2956cf7ef64738c1a3206e676
treeb4ea9ce3a8305691311974b7802f719d237a67e4
parent6a7136e6c577394e3c86a449bc07c7c4e50ce33e
experimentation to get experiment10_verilog work with FreePDK
experiments10_verilog/freepdk_c4m45/doDesign.py