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(parent: b98e51e) | patch
add GPIOs to south bank, move UART SPI SDR over by one (Mux1 column)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 28 Jun 2022 13:20:47 +0000 (14:20 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 28 Jun 2022 13:20:50 +0000 (14:20 +0100)
commitf9d1fee176fd01b68e90ec28ec508bbf77cec7de
treee385ff307b8dd57b449cd27cd2c0797802ef8da8tree
parentb98e51ea2806517b0ac5fd707ae65f1c878500facommit | diff
add GPIOs to south bank, move UART SPI SDR over by one (Mux1 column)
src/spec/ls2.py diff | blob | history
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