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(parent: 3c7bdc1) | patch
fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Jul 2020 14:53:36 +0000 (15:53 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 19 Jul 2020 14:53:36 +0000 (15:53 +0100)
commitfc256a3df6502d725131a3aa979c2a88aa695d3d
tree12ec793c34a25bb3e06d47c0bbf97b2c73f64eddtree
parent3c7bdc1cf9f1a48c9b41b153083c85b6a887a755commit | diff
fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i
src/soc/experiment/alu_fsm.py diff | blob | history
src/soc/fu/alu/test/test_pipe_caller.py diff | blob | history