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(parent: 3188f92) | patch
preserve bits of SRR1 on a TRAP (including all interrupts) which in
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 18 Jan 2022 13:42:12 +0000 (13:42 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 18 Jan 2022 13:42:12 +0000 (13:42 +0000)
commitfc576b1ebe7809053214d5a8fc022cad5a1a7a14
tree1475f26d2e73d98d9276421558fc69081a583603tree
parent3188f922c069f7958a1808652f3368a51d31a85acommit | diff
preserve bits of SRR1 on a TRAP (including all interrupts) which in
turn means that PowerDecoder2 has to read SRR1
src/soc/fu/trap/main_stage.py diff | blob | history