projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b6a9b90) | patch
adding option to include XICS external interrupts.
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 15:11:10 +0000 (16:11 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 15:11:10 +0000 (16:11 +0100)
commitffe70742b1fb287ba1766df8a8e55ec2190db797
tree0e7d808203d2f3214d8fb431748b3281af3e3b5dtree
parentb6a9b9057d6694df7f1d20d8ad073ff49e0e1355commit | diff
adding option to include XICS external interrupts.
XICS ICP and ICS are included, the wishbone slave ports added to TestIssuer
then if ext_irq is raised in core, execution jumps to 0x500 through a TRAP
src/soc/config/state.py diff | blob | history
src/soc/consts.py diff | blob | history
src/soc/decoder/power_decoder2.py diff | blob | history
src/soc/fu/trap/main_stage.py diff | blob | history
src/soc/interrupts/xics.py diff | blob | history
src/soc/litex/florent/sim.py diff | blob | history
src/soc/simple/core.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history
src/soc/simple/issuer_verilog.py diff | blob | history