Reduce ECP5 85 nest frequency to 75MHz ddr3
authorRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 11 Apr 2022 20:06:17 +0000 (15:06 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Mon, 11 Apr 2022 20:06:17 +0000 (15:06 -0500)
commit9545d27f40963c577cde883b7fc33dac47b522f7
tree166154127773a9b205ab2249aadbb13675f3591c
parent2d7021ba09c3e08e1780bf73c26deeaccf689221
Reduce ECP5 85 nest frequency to 75MHz

This gets much closer to passing timing on the
-7 speed grade parts, and should pass timing
on the -8 speed grade parts.

Verified to boot correctly:

fw..DRAM init... initseq
done
MR profile: 00000B20 00000806 00000200 00000000
Rdly
p0: 01110011
Rdly
p1: 01110011
Auto calibrating... find mindone
Auto calibration profile:p0 rdly:00000002 p1 rdly:00000002
Reloading built-in calibration profile...DRAM test...
done
src/ls2.py