- # create and connect wishbone
- self.wb = self.jtag.add_wishbone(ircodes=[5, 6, 7], features={'err'},
- address_width=30, data_width=32,
+ # decide how many SRAMs you want to create (and what sizes)
+ # simply edit this before running "make lvx"
+ # try not to go above 3 because you run out of JTAG ircodes that way.
+ # if you really really must, then increase ir_width above, first
+ self.memsizes = []
+ #self.memsizes.append((32, 32)) # width, depth
+ self.memsizes.append((32, 16)) # width, depth
+ self.memsizes.append((32, 16)) # width, depth
+
+ # create and connect wishbone(s). okok, a better solution is to
+ # use a Wishbone Arbiter, and only have one WB bus.
+ self.wb = []
+ ircode = 5 # start at 5,6,7 then jump 11,12,13 then 14,15,16 etc. etc.
+ for i, (width, depth) in enumerate(self.memsizes):
+ ircodes = [ircode, ircode+1, ircode+2]
+ if ircode == 5:
+ # next one skips DMI (see below - 8,9,10 already used)
+ ircode = 11
+ else:
+ ircode += 3
+ wb = self.jtag.add_wishbone(ircodes=ircodes, features={'err'},
+ address_width=30, data_width=width,