- # until ld_active (or st_active) are de-asserted.
-
- # if now in "LD" mode: wait for addr_ok, then send the address out
- # to memory, acknowledge address, and send out LD data
- with m.If(ld_active.q):
- # set up LenExpander with the LD len and lower bits of addr
- lsbaddr, msbaddr = self.splitaddr(ldport.addr.data)
- comb += lenexp.len_i.eq(ldport.data_len)
- comb += lenexp.addr_i.eq(lsbaddr)
- with m.If(ldport.addr.ok & adrok_l.qn):
- comb += rdport.addr.eq(msbaddr) # addr ok, send thru
- comb += ldport.addr_ok_o.eq(1) # acknowledge addr ok
- sync += adrok_l.s.eq(1) # and pull "ack" latch
-
- # if now in "ST" mode: likewise do the same but with "ST"
- # to memory, acknowledge address, and send out LD data
- with m.If(st_active.q):
- # set up LenExpander with the ST len and lower bits of addr
- lsbaddr, msbaddr = self.splitaddr(stport.addr.data)
- comb += lenexp.len_i.eq(stport.data_len)
- comb += lenexp.addr_i.eq(lsbaddr)
- with m.If(stport.addr.ok):
- comb += wrport.addr.eq(msbaddr) # addr ok, send thru
- with m.If(adrok_l.qn):
- comb += stport.addr_ok_o.eq(1) # acknowledge addr ok
- sync += adrok_l.s.eq(1) # and pull "ack" latch
-
- # NOTE: in both these, below, the port itself takes care
- # of de-asserting its "busy_o" signal, based on either ld.ok going
- # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
-
- # for LD mode, when addr has been "ok'd", assume that (because this
- # is a "Memory" test-class) the memory read data is valid.