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print out regfile unary status, bit of name-cleanup
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 16 Nov 2021 19:12:51 +0000
(19:12 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 16 Nov 2021 19:12:51 +0000
(19:12 +0000)
src/soc/simple/core.py
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diff --git
a/src/soc/simple/core.py
b/src/soc/simple/core.py
index 4e7ade872f982f807b2cdc38df4c0d2999268cc4..4a98c5faff13d7ef355315153fba09d0a9aa6fb1 100644
(file)
--- a/
src/soc/simple/core.py
+++ b/
src/soc/simple/core.py
@@
-481,14
+481,15
@@
class NonProductionCore(ControlBase):
fus = self.fus.fus
regs = self.regs
fus = self.fus.fus
regs = self.regs
- print("connect wr", regname, fspec)
rpidx = regname
# select the required write port. these are pre-defined sizes
rpidx = regname
# select the required write port. these are pre-defined sizes
- print(regfile, regs.rf.keys())
rfile = regs.rf[regfile.lower()]
wport = rfile.w_ports[rpidx]
rfile = regs.rf[regfile.lower()]
wport = rfile.w_ports[rpidx]
+ print("connect wr", regname, "unary", rfile.unary, fspec)
+ print(regfile, regs.rf.keys())
+
# select the write-protection hazard vector. note that this still
# requires to WRITE to the hazard bitvector! read-requests need
# to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
# select the write-protection hazard vector. note that this still
# requires to WRITE to the hazard bitvector! read-requests need
# to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
@@
-566,7
+567,8
@@
class NonProductionCore(ControlBase):
# connect the regspec write "reg select" number to this port
# only if one FU actually requests (and is granted) the port
# will the write-enable be activated
# connect the regspec write "reg select" number to this port
# only if one FU actually requests (and is granted) the port
# will the write-enable be activated
- addr_en = Signal.like(write)
+ wname = "waddr_en_%s_%s_%d" % (funame, regname, idx)
+ addr_en = Signal.like(write, name=wname)
wp = Signal()
comb += wp.eq(wr_pick & wrpick.en_o)
comb += addr_en.eq(Mux(wp, write, 0))
wp = Signal()
comb += wp.eq(wr_pick & wrpick.en_o)
comb += addr_en.eq(Mux(wp, write, 0))