projects
/
soc.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
1d89663
)
fix proof_datamerger (see 216#c56)
author
Tobias Platen
<tplaten@posteo.de>
Fri, 5 Jun 2020 19:18:46 +0000
(21:18 +0200)
committer
Tobias Platen
<tplaten@posteo.de>
Fri, 5 Jun 2020 19:18:46 +0000
(21:18 +0200)
src/soc/experiment/proof_datamerger.py
patch
|
blob
|
history
diff --git
a/src/soc/experiment/proof_datamerger.py
b/src/soc/experiment/proof_datamerger.py
index 6fe7aead21686c3e24b30e0d69841060c39eb4f3..dd44449e56adca0c3e3f5a1aeef74d66e127ef6e 100644
(file)
--- a/
src/soc/experiment/proof_datamerger.py
+++ b/
src/soc/experiment/proof_datamerger.py
@@
-29,8
+29,8
@@
class Driver(Elaboratable):
# assign anyseq to inputs
for j in range(dut.array_size):
# assign anyseq to inputs
for j in range(dut.array_size):
- comb += dut.addr_array_i[j].eq(Any
Seq
(dut.array_size))
- comb += dut.data_i[j].eq(Any
Seq
(16+128))
+ comb += dut.addr_array_i[j].eq(Any
Const
(dut.array_size))
+ comb += dut.data_i[j].eq(Any
Const
(16+128))
allzero = 1
for j in range(dut.array_size):
allzero = 1
for j in range(dut.array_size):
@@
-42,10
+42,10
@@
class Driver(Elaboratable):
with m.Else():
comb += Assume(dut.data_o != 0) # at least one output bit is set
for j in range(dut.array_size):
with m.Else():
comb += Assume(dut.data_o != 0) # at least one output bit is set
for j in range(dut.array_size):
- for b in range(
0,
8):
+ for b in range(8):
with m.If(dut.data_o.en[b]):
comb += Assume(dut.data_i[j].en[b])
with m.If(dut.data_o.en[b]):
comb += Assume(dut.data_i[j].en[b])
- for b in range(
0,
128):
+ for b in range(128):
with m.If(dut.data_o.data[b]):
comb += Assume(dut.data_i[j].data[b])
with m.If(dut.data_o.data[b]):
comb += Assume(dut.data_i[j].data[b])