def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
spec=None, limit=None, origsuffix=None):
def __init__(self, fname, pingroup, bankspec, suffix, offs, bank, mux,
spec=None, limit=None, origsuffix=None):
+
+ # function type can be in, out or inout, represented by - + *
+ # strip function type out of each pin name
+ self.fntype = {}
+ for i in range(len(pingroup)):
+ pname = pingroup[i]
+ if not pname:
+ continue
+ fntype = pname[-1]
+ if fntype not in '+-*':
+ continue
+ pname = pname[:-1]
+ fntype = {'-': 'in', '+': 'out', '*': 'inout'}[fntype]
+ self.fntype[pname] = fntype
+ pingroup[i] = pname
+
def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- i2spins = ['MCK', 'BCK', 'LRCK', 'DI']
+ i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-']
return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
start=None, limit=None):
return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
start=None, limit=None):
sdmmcpins = sdmmcpins[start:limit]
return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
sdmmcpins = sdmmcpins[start:limit]
return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS']
+ spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- spipins = ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3']
+ spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('QSPI', spipins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['MS', 'DI', 'DO', 'CK']
- return Pins('JTAG', uartpins, bankspec, suffix, offs, bank, mux, spec,
+ jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
+ return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
origsuffix=suffix)
def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
return names
def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
return names
def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
- ulpipins = ['CK', 'DIR', 'STP', 'NXT']
+ ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX', 'RX', 'CTS', 'RTS']
+ uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
- ttlpins = ['CK', 'DE', 'HS', 'VS']
+ ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(4):
return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(4):
- buspins.append("ETXD%d" % i)
- buspins += ['ERXCK', 'ERXERR', 'ERXDV',
- 'EMDC', 'EMDIO',
- 'ETXEN', 'ETXCK', 'ECRS',
- 'ECOL', 'ETXERR']
+ buspins.append("ETXD%d+" % i)
+ buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
+ 'EMDC+', 'EMDIO*',
+ 'ETXEN+', 'ETXCK+', 'ECRS-',
+ 'ECOL+', 'ETXERR+']
return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(8):
return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(8):
- buspins.append("CS%d" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK',
+ buspins.append("CS%d+" % i)
+ buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
'A0', 'A1', 'TS', 'TBST',
'TSIZ0', 'TSIZ1']
for i in range(4):
buspins.append("BWE%d" % i)
for i in range(2,6):
'A0', 'A1', 'TS', 'TBST',
'TSIZ0', 'TSIZ1']
for i in range(4):
buspins.append("BWE%d" % i)
for i in range(2,6):
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(8,32):
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(8,32):
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(16):
return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(16):
- buspins.append("SDRBA%d" % i)
- buspins += ['SDRCKE', 'SDRRAS#', 'SDRCAS#', 'SDRWE#',
- 'SDRRST']
+ buspins.append("SDRBA%d+" % i)
+ buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
+ 'SDRRST+']
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(3,6):
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
buspins = []
for i in range(3,6):
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(8):
return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
origsuffix=suffix)
def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
buspins = []
for i in range(8):
- buspins.append("MCUNRB%d" % i)
- buspins += ['MCUCD', 'MCURD', 'MCUWR', 'MCUCLE', 'MCUALE',
- 'MCURST']
+ buspins.append("MCUNRB%d+" % i)
+ buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
+ 'MCURST+']
return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
gpiopins = []
for i in range(gpiooffs, gpiooffs+gpionum):
return Pins('GPIO', gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
gpiopins = []
for i in range(gpiooffs, gpiooffs+gpionum):
return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def pwm(bankspec, suffix, offs, bank, mux=1, spec=None):
- return Pins('PWM', ['', ], bankspec, suffix, offs, bank, mux, spec,
+ return Pins('PWM', ['+', ], bankspec, suffix, offs, bank, mux, spec,
origsuffix=suffix)
def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
origsuffix=suffix)
def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):