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add tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 4 Apr 2022 21:32:32 +0000
(22:32 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 4 Apr 2022 21:32:32 +0000
(22:32 +0100)
src/soc/bus/uart_16550.py
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diff --git
a/src/soc/bus/uart_16550.py
b/src/soc/bus/uart_16550.py
index 366696e977a0993d603eb7fafedcf57e333dce25..bceec5e29249b0048f0d0ca936b5b10243cc7505 100644
(file)
--- a/
src/soc/bus/uart_16550.py
+++ b/
src/soc/bus/uart_16550.py
@@
-13,6
+13,7
@@
from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
from nmigen_soc.wishbone.bus import Interface
from nmigen.cli import rtlil, verilog
import os
from nmigen_soc.wishbone.bus import Interface
from nmigen.cli import rtlil, verilog
import os
+import tempfile
__all__ = ["UART16550"]
__all__ = ["UART16550"]
@@
-63,6
+64,13
@@
class UART16550(Elaboratable):
@classmethod
def add_verilog_source(cls, verilog_src_dir, platform):
@classmethod
def add_verilog_source(cls, verilog_src_dir, platform):
+ # create a temp file containing "`define DATA_BUS_WIDTH_8"
+ t = tempfile.NamedTemporaryFile(delete=False, suffix=".v")
+ t.write("`define DATA_BUS_WIDTH_8\n".encode())
+ t.flush()
+ t.seek(0)
+ platform.add_file(t.name, t)
+
# add each of the verilog sources, needed for when doing platform.build
for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
'uart_top.v', 'timescale.v', 'uart_receiver.v',
# add each of the verilog sources, needed for when doing platform.build
for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
'uart_top.v', 'timescale.v', 'uart_receiver.v',