- with m.If(insn_type != InternalOp.OP_NOP):
- comb += core_ivalid_i.eq(1) # say instruction is valid
- comb += core_opcode_i.eq(ilatch) # actual opcode
- with m.If(self.fast_nia.wen):
- sync += pc_changed.eq(1)
- with m.If(~core_busy_o): # instruction done!
- # ok here we are not reading the branch unit. TODO
- # this just blithely overwrites whatever pipeline
- # updated the PC
- with m.If(~pc_changed):
- comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
- comb += self.fast_wr1.data_i.eq(nia)
- m.next = "IDLE" # back to idle
+ with m.If(core.core_terminated_o):
+ m.next = "IDLE" # back to idle, immediately (OP_ATTN)
+ with m.Else():
+ with m.If(insn_type != InternalOp.OP_NOP):
+ comb += core_ivalid_i.eq(1) # instruction is valid
+ comb += core_opcode_i.eq(ilatch) # actual opcode
+ with m.If(self.fast_nia.wen):
+ sync += pc_changed.eq(1)
+ with m.If(~core_busy_o): # instruction done!
+ # ok here we are not reading the branch unit. TODO
+ # this just blithely overwrites whatever pipeline
+ # updated the PC
+ with m.If(~pc_changed):
+ comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
+ comb += self.fast_wr1.data_i.eq(nia)
+ m.next = "IDLE" # back to idle