from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance,
from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance,
cd_sync2x = ClockDomain("sync2x", local=False)
cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
local=False, reset_less=True)
cd_init = ClockDomain("init", local=False)
cd_sync = ClockDomain("sync", local=False)
cd_dramsync = ClockDomain("dramsync", local=False)
cd_sync2x = ClockDomain("sync2x", local=False)
cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
local=False, reset_less=True)
cd_init = ClockDomain("init", local=False)
cd_sync = ClockDomain("sync", local=False)
cd_dramsync = ClockDomain("dramsync", local=False)
pll.create_clkout(ClockSignal("sync2x_unbuf"), 2*self.sys_clk_freq)
pll.create_clkout(ClockSignal("init"), 25e6)
m.submodules += Instance("ECLKSYNCB",
pll.create_clkout(ClockSignal("sync2x_unbuf"), 2*self.sys_clk_freq)
pll.create_clkout(ClockSignal("init"), 25e6)
m.submodules += Instance("ECLKSYNCB",