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do not clear out ldst request after TLB entry is added
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 8 Jan 2022 16:49:27 +0000
(16:49 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 8 Jan 2022 16:49:27 +0000
(16:49 +0000)
src/soc/fu/ldst/loadstore.py
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diff --git
a/src/soc/fu/ldst/loadstore.py
b/src/soc/fu/ldst/loadstore.py
index 407abeb14378c230a8529cbf70c2e23259766892..ce77353a74bb792d1cb773d3c301e9bce05c3061 100644
(file)
--- a/
src/soc/fu/ldst/loadstore.py
+++ b/
src/soc/fu/ldst/loadstore.py
@@
-330,7
+330,6
@@
class LoadStore1(PortInterfaceBase):
# installed a TLB entry, if not exception raised
m.d.comb += self.d_out.valid.eq(~exception)
sync += self.state.eq(State.ACK_WAIT)
# installed a TLB entry, if not exception raised
m.d.comb += self.d_out.valid.eq(~exception)
sync += self.state.eq(State.ACK_WAIT)
- sync += ldst_r.eq(0)
with m.Else():
sync += self.state.eq(State.IDLE)
sync += self.r_instr_fault.eq(0)
with m.Else():
sync += self.state.eq(State.IDLE)
sync += self.r_instr_fault.eq(0)
@@
-440,10
+439,6
@@
class LoadStore1(PortInterfaceBase):
#m.d.comb += Display("no_validblip dcbz=%i addr=%x",
#ldst_r.dcbz,ldst_r.addr)
m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
#m.d.comb += Display("no_validblip dcbz=%i addr=%x",
#ldst_r.dcbz,ldst_r.addr)
m.d.comb += d_out.dcbz.eq(ldst_r.dcbz)
-
- # XXX these should be possible to remove but for some reason
- # cannot be... yet. TODO, investigate
- #m.d.comb += self.load_data.eq(d_in.data)
m.d.comb += d_out.addr.eq(self.raddr)
# Update outputs to MMU
m.d.comb += d_out.addr.eq(self.raddr)
# Update outputs to MMU