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replace i_data with data_i and o_data with data_o
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 27 Apr 2019 14:08:06 +0000
(15:08 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 27 Apr 2019 14:08:06 +0000
(15:08 +0100)
src/add/fpbase.py
patch
|
blob
|
history
src/add/fpcommon/getop.py
patch
|
blob
|
history
src/add/multipipe.py
patch
|
blob
|
history
src/add/singlepipe.py
patch
|
blob
|
history
src/add/test_buf_pipe.py
patch
|
blob
|
history
src/add/test_fpadd_pipe.py
patch
|
blob
|
history
src/add/test_fsm_experiment.py
patch
|
blob
|
history
src/add/test_inout_mux_pipe.py
patch
|
blob
|
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src/add/test_outmux_pipe.py
patch
|
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src/add/test_prioritymux_pipe.py
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diff --git
a/src/add/fpbase.py
b/src/add/fpbase.py
index 3519760827f29098e03c7e65fd1c424709a4d08a..c707f1ac23ecfc7433ddc823a95e2e1a7e07a057 100644
(file)
--- a/
src/add/fpbase.py
+++ b/
src/add/fpbase.py
@@
-490,7
+490,7
@@
class FPOpIn(PrevControl):
PrevControl.__init__(self)
self.width = width
self.v = Signal(width)
PrevControl.__init__(self)
self.width = width
self.v = Signal(width)
- self.
i_data
= self.v
+ self.
data_i
= self.v
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
@@
-516,7
+516,7
@@
class FPOpOut(NextControl):
NextControl.__init__(self)
self.width = width
self.v = Signal(width)
NextControl.__init__(self)
self.width = width
self.v = Signal(width)
- self.
o_data
= self.v
+ self.
data_o
= self.v
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
diff --git
a/src/add/fpcommon/getop.py
b/src/add/fpcommon/getop.py
index b966ecbd09f5861f502399a7a62c8a7a042962b6..8cb9521bb3f0e9837588a9f7942dab45628b0b3e 100644
(file)
--- a/
src/add/fpcommon/getop.py
+++ b/
src/add/fpcommon/getop.py
@@
-101,8
+101,8
@@
class FPGet2OpMod(PrevControl):
PrevControl.__init__(self)
self.width = width
self.id_wid = id_wid
PrevControl.__init__(self)
self.width = width
self.id_wid = id_wid
- self.
i_data
= self.ispec()
- self.i = self.
i_data
+ self.
data_i
= self.ispec()
+ self.i = self.
data_i
self.o = self.ospec()
def ispec(self):
self.o = self.ospec()
def ispec(self):
@@
-118,7
+118,7
@@
class FPGet2OpMod(PrevControl):
m = PrevControl.elaborate(self, platform)
with m.If(self.trigger):
m.d.comb += [
m = PrevControl.elaborate(self, platform)
with m.If(self.trigger):
m.d.comb += [
- self.o.eq(self.
i_data
),
+ self.o.eq(self.
data_i
),
]
return m
]
return m
diff --git
a/src/add/multipipe.py
b/src/add/multipipe.py
index d679f7b21e9437f797dd38fec98bee725ca9e5de..3235359dc84a917785d559755f769362649862de 100644
(file)
--- a/
src/add/multipipe.py
+++ b/
src/add/multipipe.py
@@
-32,8
+32,8
@@
class MultiInControlBase(Elaboratable):
* n: contains ready/valid to the next stage
User must also:
* n: contains ready/valid to the next stage
User must also:
- * add
i_data
members to PrevControl and
- * add
o_data
member to NextControl
+ * add
data_i
members to PrevControl and
+ * add
data_o
member to NextControl
"""
# set up input and output IO ACK (prev/next ready/valid)
p = []
"""
# set up input and output IO ACK (prev/next ready/valid)
p = []
@@
-66,7
+66,7
@@
class MultiInControlBase(Elaboratable):
def set_input(self, i, idx=0):
""" helper function to set the input data
"""
def set_input(self, i, idx=0):
""" helper function to set the input data
"""
- return eq(self.p[idx].
i_data
, i)
+ return eq(self.p[idx].
data_i
, i)
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
@@
-96,8
+96,8
@@
class MultiOutControlBase(Elaboratable):
* n: contains ready/valid to the next stages PLURAL
User must also:
* n: contains ready/valid to the next stages PLURAL
User must also:
- * add
i_data
member to PrevControl and
- * add
o_data
members to NextControl
+ * add
data_i
member to PrevControl and
+ * add
data_o
members to NextControl
"""
# set up input and output IO ACK (prev/next ready/valid)
"""
# set up input and output IO ACK (prev/next ready/valid)
@@
-136,7
+136,7
@@
class MultiOutControlBase(Elaboratable):
def set_input(self, i):
""" helper function to set the input data
"""
def set_input(self, i):
""" helper function to set the input data
"""
- return eq(self.p.
i_data
, i)
+ return eq(self.p.
data_i
, i)
def __iter__(self):
yield from self.p
def __iter__(self):
yield from self.p
@@
-152,8
+152,8
@@
class CombMultiOutPipeline(MultiOutControlBase):
Attributes:
-----------
Attributes:
-----------
- p.
i_data
: stage input data (non-array). shaped according to ispec
- n.
o_data
: stage output data array. shaped according to ospec
+ p.
data_i
: stage input data (non-array). shaped according to ispec
+ n.
data_o
: stage output data array. shaped according to ospec
"""
def __init__(self, stage, n_len, n_mux):
"""
def __init__(self, stage, n_len, n_mux):
@@
-162,9
+162,9
@@
class CombMultiOutPipeline(MultiOutControlBase):
self.n_mux = n_mux
# set up the input and output data
self.n_mux = n_mux
# set up the input and output data
- self.p.
i_data
= stage.ispec() # input type
+ self.p.
data_i
= stage.ispec() # input type
for i in range(n_len):
for i in range(n_len):
- self.n[i].
o_data
= stage.ospec() # output type
+ self.n[i].
data_o
= stage.ospec() # output type
def elaborate(self, platform):
m = MultiOutControlBase.elaborate(self, platform)
def elaborate(self, platform):
m = MultiOutControlBase.elaborate(self, platform)
@@
-195,8
+195,8
@@
class CombMultiOutPipeline(MultiOutControlBase):
m.d.comb += data_valid.eq(p_valid_i | \
(~self.n[mid].ready_i & data_valid))
with m.If(pv):
m.d.comb += data_valid.eq(p_valid_i | \
(~self.n[mid].ready_i & data_valid))
with m.If(pv):
- m.d.comb += eq(r_data, self.p.
i_data
)
- m.d.comb += eq(self.n[mid].
o_data
, self.stage.process(r_data))
+ m.d.comb += eq(r_data, self.p.
data_i
)
+ m.d.comb += eq(self.n[mid].
data_o
, self.stage.process(r_data))
return m
return m
@@
-206,9
+206,9
@@
class CombMultiInPipeline(MultiInControlBase):
Attributes:
-----------
Attributes:
-----------
- p.
i_data
: StageInput, shaped according to ispec
+ p.
data_i
: StageInput, shaped according to ispec
The pipeline input
The pipeline input
- p.
o_data
: StageOutput, shaped according to ospec
+ p.
data_o
: StageOutput, shaped according to ospec
The pipeline output
r_data : input_shape according to ispec
A temporary (buffered) copy of a prior (valid) input.
The pipeline output
r_data : input_shape according to ispec
A temporary (buffered) copy of a prior (valid) input.
@@
-223,8
+223,8
@@
class CombMultiInPipeline(MultiInControlBase):
# set up the input and output data
for i in range(p_len):
# set up the input and output data
for i in range(p_len):
- self.p[i].
i_data
= stage.ispec() # input type
- self.n.
o_data
= stage.ospec()
+ self.p[i].
data_i
= stage.ispec() # input type
+ self.n.
data_o
= stage.ospec()
def elaborate(self, platform):
m = MultiInControlBase.elaborate(self, platform)
def elaborate(self, platform):
m = MultiInControlBase.elaborate(self, platform)
@@
-275,9
+275,9
@@
class CombMultiInPipeline(MultiInControlBase):
vr = Signal(reset_less=True)
m.d.comb += vr.eq(self.p[i].valid_i & self.p[i].ready_o)
with m.If(vr):
vr = Signal(reset_less=True)
m.d.comb += vr.eq(self.p[i].valid_i & self.p[i].ready_o)
with m.If(vr):
- m.d.comb += eq(r_data[i], self.p[i].
i_data
)
+ m.d.comb += eq(r_data[i], self.p[i].
data_i
)
- m.d.comb += eq(self.n.
o_data
, self.stage.process(r_data[mid]))
+ m.d.comb += eq(self.n.
data_o
, self.stage.process(r_data[mid]))
return m
return m
@@
-288,7
+288,7
@@
class CombMuxOutPipe(CombMultiOutPipeline):
CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
# HACK: n-mux is also the stage... so set the muxid equal to input mid
CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
# HACK: n-mux is also the stage... so set the muxid equal to input mid
- stage.m_id = self.p.
i_data
.mid
+ stage.m_id = self.p.
data_i
.mid
diff --git
a/src/add/singlepipe.py
b/src/add/singlepipe.py
index e3e89167514981455058a367915611c1846f2f15..6ee0bb96a2130cb704f4152bba041d78075871f2 100644
(file)
--- a/
src/add/singlepipe.py
+++ b/
src/add/singlepipe.py
@@
-269,14
+269,14
@@
class PrevControl(Elaboratable):
may be a multi-bit signal, where all bits are required
to be asserted to indicate "valid".
* ready_o: output to next stage indicating readiness to accept data
may be a multi-bit signal, where all bits are required
to be asserted to indicate "valid".
* ready_o: output to next stage indicating readiness to accept data
- *
i_data
: an input - added by the user of this class
+ *
data_i
: an input - added by the user of this class
"""
def __init__(self, i_width=1, stage_ctl=False):
self.stage_ctl = stage_ctl
self.valid_i = Signal(i_width, name="p_valid_i") # prev >>in self
self._ready_o = Signal(name="p_ready_o") # prev <<out self
"""
def __init__(self, i_width=1, stage_ctl=False):
self.stage_ctl = stage_ctl
self.valid_i = Signal(i_width, name="p_valid_i") # prev >>in self
self._ready_o = Signal(name="p_ready_o") # prev <<out self
- self.
i_data
= None # XXX MUST BE ADDED BY USER
+ self.
data_i
= None # XXX MUST BE ADDED BY USER
if stage_ctl:
self.s_ready_o = Signal(name="p_s_o_rdy") # prev <<out self
self.trigger = Signal(reset_less=True)
if stage_ctl:
self.s_ready_o = Signal(name="p_s_o_rdy") # prev <<out self
self.trigger = Signal(reset_less=True)
@@
-294,10
+294,10
@@
class PrevControl(Elaboratable):
do not use to connect stage-to-stage!
"""
valid_i = prev.valid_i if direct else prev.valid_i_test
do not use to connect stage-to-stage!
"""
valid_i = prev.valid_i if direct else prev.valid_i_test
- i_data = fn(prev.i_data) if fn is not None else prev.i_data
+ data_i = fn(prev.data_i) if fn is not None else prev.data_i
return [self.valid_i.eq(valid_i),
prev.ready_o.eq(self.ready_o),
return [self.valid_i.eq(valid_i),
prev.ready_o.eq(self.ready_o),
- eq(self.
i_data, i_data
),
+ eq(self.
data_i, data_i
),
]
@property
]
@property
@@
-324,19
+324,19
@@
class PrevControl(Elaboratable):
return m
def eq(self, i):
return m
def eq(self, i):
- return [self.
i_data.eq(i.i_data
),
+ return [self.
data_i.eq(i.data_i
),
self.ready_o.eq(i.ready_o),
self.valid_i.eq(i.valid_i)]
def __iter__(self):
yield self.valid_i
yield self.ready_o
self.ready_o.eq(i.ready_o),
self.valid_i.eq(i.valid_i)]
def __iter__(self):
yield self.valid_i
yield self.ready_o
- if hasattr(self.
i_data
, "ports"):
- yield from self.
i_data
.ports()
- elif isinstance(self.
i_data
, Sequence):
- yield from self.
i_data
+ if hasattr(self.
data_i
, "ports"):
+ yield from self.
data_i
.ports()
+ elif isinstance(self.
data_i
, Sequence):
+ yield from self.
data_i
else:
else:
- yield self.
i_data
+ yield self.
data_i
def ports(self):
return list(self)
def ports(self):
return list(self)
@@
-346,13
+346,13
@@
class NextControl(Elaboratable):
""" contains the signals that go *to* the next stage (both in and out)
* valid_o: output indicating to next stage that data is valid
* ready_i: input from next stage indicating that it can accept data
""" contains the signals that go *to* the next stage (both in and out)
* valid_o: output indicating to next stage that data is valid
* ready_i: input from next stage indicating that it can accept data
- *
o_data
: an output - added by the user of this class
+ *
data_o
: an output - added by the user of this class
"""
def __init__(self, stage_ctl=False):
self.stage_ctl = stage_ctl
self.valid_o = Signal(name="n_valid_o") # self out>> next
self.ready_i = Signal(name="n_ready_i") # self <<in next
"""
def __init__(self, stage_ctl=False):
self.stage_ctl = stage_ctl
self.valid_o = Signal(name="n_valid_o") # self out>> next
self.ready_i = Signal(name="n_ready_i") # self <<in next
- self.
o_data
= None # XXX MUST BE ADDED BY USER
+ self.
data_o
= None # XXX MUST BE ADDED BY USER
#if self.stage_ctl:
self.d_valid = Signal(reset=1) # INTERNAL (data valid)
self.trigger = Signal(reset_less=True)
#if self.stage_ctl:
self.d_valid = Signal(reset=1) # INTERNAL (data valid)
self.trigger = Signal(reset_less=True)
@@
-370,7
+370,7
@@
class NextControl(Elaboratable):
"""
return [nxt.valid_i.eq(self.valid_o),
self.ready_i.eq(nxt.ready_o),
"""
return [nxt.valid_i.eq(self.valid_o),
self.ready_i.eq(nxt.ready_o),
- eq(nxt.
i_data, self.o_data
),
+ eq(nxt.
data_i, self.data_o
),
]
def _connect_out(self, nxt, direct=False, fn=None):
]
def _connect_out(self, nxt, direct=False, fn=None):
@@
-378,10
+378,10
@@
class NextControl(Elaboratable):
do not use to connect stage-to-stage!
"""
ready_i = nxt.ready_i if direct else nxt.ready_i_test
do not use to connect stage-to-stage!
"""
ready_i = nxt.ready_i if direct else nxt.ready_i_test
- o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
+ data_o = fn(nxt.data_o) if fn is not None else nxt.data_o
return [nxt.valid_o.eq(self.valid_o),
self.ready_i.eq(ready_i),
return [nxt.valid_o.eq(self.valid_o),
self.ready_i.eq(ready_i),
- eq(
o_data, self.o_data
),
+ eq(
data_o, self.data_o
),
]
def elaborate(self, platform):
]
def elaborate(self, platform):
@@
-392,12
+392,12
@@
class NextControl(Elaboratable):
def __iter__(self):
yield self.ready_i
yield self.valid_o
def __iter__(self):
yield self.ready_i
yield self.valid_o
- if hasattr(self.
o_data
, "ports"):
- yield from self.
o_data
.ports()
- elif isinstance(self.
o_data
, Sequence):
- yield from self.
o_data
+ if hasattr(self.
data_o
, "ports"):
+ yield from self.
data_o
.ports()
+ elif isinstance(self.
data_o
, Sequence):
+ yield from self.
data_o
else:
else:
- yield self.
o_data
+ yield self.
data_o
def ports(self):
return list(self)
def ports(self):
return list(self)
@@
-672,8
+672,8
@@
class ControlBase(Elaboratable):
* n: contains ready/valid to the next stage
Except when calling Controlbase.connect(), user must also:
* n: contains ready/valid to the next stage
Except when calling Controlbase.connect(), user must also:
- * add
i_data
member to PrevControl (p) and
- * add
o_data
member to NextControl (n)
+ * add
data_i
member to PrevControl (p) and
+ * add
data_o
member to NextControl (n)
"""
self.stage = stage
"""
self.stage = stage
@@
-683,8
+683,8
@@
class ControlBase(Elaboratable):
# set up the input and output data
if stage is not None:
# set up the input and output data
if stage is not None:
- self.p.
i_data = _spec(stage.ispec, "i_data
") # input type
- self.n.
o_data = _spec(stage.ospec, "o_data
") # output type
+ self.p.
data_i = _spec(stage.ispec, "data_i
") # input type
+ self.n.
data_o = _spec(stage.ospec, "data_o
") # output type
def connect_to_next(self, nxt):
""" helper function to connect to the next stage data/valid/ready.
def connect_to_next(self, nxt):
""" helper function to connect to the next stage data/valid/ready.
@@
-715,9
+715,9
@@
class ControlBase(Elaboratable):
v | v | v |
out---in out--in out---in
v | v | v |
out---in out--in out---in
- Also takes care of allocating
i_data/o_data
, by looking up
+ Also takes care of allocating
data_i/data_o
, by looking up
the data spec for each end of the pipechain. i.e It is NOT
the data spec for each end of the pipechain. i.e It is NOT
- necessary to allocate self.p.
i_data or self.n.o_data
manually:
+ necessary to allocate self.p.
data_i or self.n.data_o
manually:
this is handled AUTOMATICALLY, here.
Basically this function is the direct equivalent of StageChain,
this is handled AUTOMATICALLY, here.
Basically this function is the direct equivalent of StageChain,
@@
-743,12
+743,12
@@
class ControlBase(Elaboratable):
# connect front of chain to ourselves
front = pipechain[0]
# connect front of chain to ourselves
front = pipechain[0]
- self.p.
i_data
= _spec(front.stage.ispec, "chainin")
+ self.p.
data_i
= _spec(front.stage.ispec, "chainin")
eqs += front._connect_in(self)
# connect end of chain to ourselves
end = pipechain[-1]
eqs += front._connect_in(self)
# connect end of chain to ourselves
end = pipechain[-1]
- self.n.
o_data
= _spec(end.stage.ospec, "chainout")
+ self.n.
data_o
= _spec(end.stage.ospec, "chainout")
eqs += end._connect_out(self)
return eqs
eqs += end._connect_out(self)
return eqs
@@
-762,7
+762,7
@@
class ControlBase(Elaboratable):
def set_input(self, i):
""" helper function to set the input data
"""
def set_input(self, i):
""" helper function to set the input data
"""
- return eq(self.p.
i_data
, i)
+ return eq(self.p.
data_i
, i)
def __iter__(self):
yield from self.p
def __iter__(self):
yield from self.p
@@
-779,7
+779,7
@@
class ControlBase(Elaboratable):
m.submodules.n = self.n
if self.stage is not None and hasattr(self.stage, "setup"):
m.submodules.n = self.n
if self.stage is not None and hasattr(self.stage, "setup"):
- self.stage.setup(m, self.p.
i_data
)
+ self.stage.setup(m, self.p.
data_i
)
if not self.p.stage_ctl:
return m
if not self.p.stage_ctl:
return m
@@
-803,13
+803,13
@@
class BufferedHandshake(ControlBase):
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.
i_data >>in stage n.o_data
out>> stage+1
+ stage-1 p.
data_i >>in stage n.data_o
out>> stage+1
| |
process --->----^
| |
+-- r_data ->-+
| |
process --->----^
| |
+-- r_data ->-+
- input data p.
i_data
is read (only), is processed and goes into an
+ input data p.
data_i
is read (only), is processed and goes into an
intermediate result store [process()]. this is updated combinatorially.
in a non-stall condition, the intermediate result will go into the
intermediate result store [process()]. this is updated combinatorially.
in a non-stall condition, the intermediate result will go into the
@@
-852,7
+852,7
@@
class BufferedHandshake(ControlBase):
]
# store result of processing in combinatorial temporary
]
# store result of processing in combinatorial temporary
- self.m.d.comb += eq(result, self.stage.process(self.p.
i_data
))
+ self.m.d.comb += eq(result, self.stage.process(self.p.
data_i
))
# if not in stall condition, update the temporary register
with self.m.If(self.p.ready_o): # not stalled
# if not in stall condition, update the temporary register
with self.m.If(self.p.ready_o): # not stalled
@@
-860,16
+860,16
@@
class BufferedHandshake(ControlBase):
# data pass-through conditions
with self.m.If(npnn):
# data pass-through conditions
with self.m.If(npnn):
-
o_data
= self._postprocess(result)
+
data_o
= self._postprocess(result)
self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
self.m.d.sync += [self.n.valid_o.eq(p_valid_i), # valid if p_valid
- eq(self.n.
o_data, o_data
), # update output
+ eq(self.n.
data_o, data_o
), # update output
]
# buffer flush conditions (NOTE: can override data passthru conditions)
with self.m.If(nir_por_n): # not stalled
# Flush the [already processed] buffer to the output port.
]
# buffer flush conditions (NOTE: can override data passthru conditions)
with self.m.If(nir_por_n): # not stalled
# Flush the [already processed] buffer to the output port.
-
o_data
= self._postprocess(r_data)
+
data_o
= self._postprocess(r_data)
self.m.d.sync += [self.n.valid_o.eq(1), # reg empty
self.m.d.sync += [self.n.valid_o.eq(1), # reg empty
- eq(self.n.
o_data, o_data
), # flush buffer
+ eq(self.n.
data_o, data_o
), # flush buffer
]
# output ready conditions
self.m.d.sync += self.p._ready_o.eq(nir_novn | por_pivn)
]
# output ready conditions
self.m.d.sync += self.p._ready_o.eq(nir_novn | por_pivn)
@@
-885,7
+885,7
@@
class SimpleHandshake(ControlBase):
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.
i_data >>in stage n.o_data
out>> stage+1
+ stage-1 p.
data_i >>in stage n.data_o
out>> stage+1
| |
+--process->--^
Truth Table
| |
+--process->--^
Truth Table
@@
-899,23
+899,23
@@
class SimpleHandshake(ControlBase):
------- - - - -
0 0 0 0 0 0 >0 0 reg
0 0 0 1 0 1 >1 0 reg
------- - - - -
0 0 0 0 0 0 >0 0 reg
0 0 0 1 0 1 >1 0 reg
- 0 0 1 0 0 0 0 1 process(
i_data
)
- 0 0 1 1 0 0 0 1 process(
i_data
)
+ 0 0 1 0 0 0 0 1 process(
data_i
)
+ 0 0 1 1 0 0 0 1 process(
data_i
)
------- - - - -
0 1 0 0 0 0 >0 0 reg
0 1 0 1 0 1 >1 0 reg
------- - - - -
0 1 0 0 0 0 >0 0 reg
0 1 0 1 0 1 >1 0 reg
- 0 1 1 0 0 0 0 1 process(
i_data
)
- 0 1 1 1 0 0 0 1 process(
i_data
)
+ 0 1 1 0 0 0 0 1 process(
data_i
)
+ 0 1 1 1 0 0 0 1 process(
data_i
)
------- - - - -
1 0 0 0 0 0 >0 0 reg
1 0 0 1 0 1 >1 0 reg
------- - - - -
1 0 0 0 0 0 >0 0 reg
1 0 0 1 0 1 >1 0 reg
- 1 0 1 0 0 0 0 1 process(
i_data
)
- 1 0 1 1 0 0 0 1 process(
i_data
)
+ 1 0 1 0 0 0 0 1 process(
data_i
)
+ 1 0 1 1 0 0 0 1 process(
data_i
)
------- - - - -
------- - - - -
- 1 1 0 0 1 0 1 0 process(
i_data
)
- 1 1 0 1 1 1 1 0 process(
i_data
)
- 1 1 1 0 1 0 1 1 process(
i_data
)
- 1 1 1 1 1 0 1 1 process(
i_data
)
+ 1 1 0 0 1 0 1 0 process(
data_i
)
+ 1 1 0 1 1 1 1 0 process(
data_i
)
+ 1 1 1 0 1 0 1 1 process(
data_i
)
+ 1 1 1 1 1 0 1 1 process(
data_i
)
------- - - - -
"""
------- - - - -
"""
@@
-935,18
+935,18
@@
class SimpleHandshake(ControlBase):
]
# store result of processing in combinatorial temporary
]
# store result of processing in combinatorial temporary
- m.d.comb += eq(result, self.stage.process(self.p.
i_data
))
+ m.d.comb += eq(result, self.stage.process(self.p.
data_i
))
# previous valid and ready
with m.If(p_valid_i_p_ready_o):
# previous valid and ready
with m.If(p_valid_i_p_ready_o):
-
o_data
= self._postprocess(result)
+
data_o
= self._postprocess(result)
m.d.sync += [r_busy.eq(1), # output valid
m.d.sync += [r_busy.eq(1), # output valid
- eq(self.n.
o_data, o_data
), # update output
+ eq(self.n.
data_o, data_o
), # update output
]
# previous invalid or not ready, however next is accepting
with m.Elif(n_ready_i):
]
# previous invalid or not ready, however next is accepting
with m.Elif(n_ready_i):
-
o_data
= self._postprocess(result)
- m.d.sync += [eq(self.n.
o_data, o_data
)]
+
data_o
= self._postprocess(result)
+ m.d.sync += [eq(self.n.
data_o, data_o
)]
# TODO: could still send data here (if there was any)
#m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
m.d.sync += r_busy.eq(0) # ...so set output invalid
# TODO: could still send data here (if there was any)
#m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
m.d.sync += r_busy.eq(0) # ...so set output invalid
@@
-974,7
+974,7
@@
class UnbufferedPipeline(ControlBase):
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.
i_data >>in stage n.o_data
out>> stage+1
+ stage-1 p.
data_i >>in stage n.data_o
out>> stage+1
| |
r_data result
| |
| |
r_data result
| |
@@
-982,9
+982,9
@@
class UnbufferedPipeline(ControlBase):
Attributes:
-----------
Attributes:
-----------
- p.
i_data
: StageInput, shaped according to ispec
+ p.
data_i
: StageInput, shaped according to ispec
The pipeline input
The pipeline input
- p.
o_data
: StageOutput, shaped according to ospec
+ p.
data_o
: StageOutput, shaped according to ospec
The pipeline output
r_data : input_shape according to ispec
A temporary (buffered) copy of a prior (valid) input.
The pipeline output
r_data : input_shape according to ispec
A temporary (buffered) copy of a prior (valid) input.
@@
-1018,10
+1018,10
@@
class UnbufferedPipeline(ControlBase):
1 0 1 0 0 1 1 reg
1 0 1 1 0 1 1 reg
------- - - -
1 0 1 0 0 1 1 reg
1 0 1 1 0 1 1 reg
------- - - -
- 1 1 0 0 0 1 1 process(
i_data
)
- 1 1 0 1 1 1 0 process(
i_data
)
- 1 1 1 0 0 1 1 process(
i_data
)
- 1 1 1 1 0 1 1 process(
i_data
)
+ 1 1 0 0 0 1 1 process(
data_i
)
+ 1 1 0 1 1 1 0 process(
data_i
)
+ 1 1 1 0 0 1 1 process(
data_i
)
+ 1 1 1 1 0 1 1 process(
data_i
)
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
@@
-1046,9
+1046,9
@@
class UnbufferedPipeline(ControlBase):
m.d.sync += data_valid.eq(p_valid_i | buf_full)
with m.If(pv):
m.d.sync += data_valid.eq(p_valid_i | buf_full)
with m.If(pv):
- m.d.sync += eq(r_data, self.stage.process(self.p.
i_data
))
-
o_data
= self._postprocess(r_data)
- m.d.comb += eq(self.n.
o_data, o_data
)
+ m.d.sync += eq(r_data, self.stage.process(self.p.
data_i
))
+
data_o
= self._postprocess(r_data)
+ m.d.comb += eq(self.n.
data_o, data_o
)
return self.m
return self.m
@@
-1068,14
+1068,14
@@
class UnbufferedPipeline2(ControlBase):
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
- stage-1 p.
i_data >>in stage n.o_data
out>> stage+1
+ stage-1 p.
data_i >>in stage n.data_o
out>> stage+1
| | |
+- process-> buf <-+
Attributes:
-----------
| | |
+- process-> buf <-+
Attributes:
-----------
- p.
i_data
: StageInput, shaped according to ispec
+ p.
data_i
: StageInput, shaped according to ispec
The pipeline input
The pipeline input
- p.
o_data
: StageOutput, shaped according to ospec
+ p.
data_o
: StageOutput, shaped according to ospec
The pipeline output
buf : output_shape according to ospec
A temporary (buffered) copy of a valid output
The pipeline output
buf : output_shape according to ospec
A temporary (buffered) copy of a valid output
@@
-1089,25
+1089,25
@@
class UnbufferedPipeline2(ControlBase):
V R R V V R
------- - - -
V R R V V R
------- - - -
- 0 0 0 0 0 0 1 process(
i_data
)
+ 0 0 0 0 0 0 1 process(
data_i
)
0 0 0 1 1 1 0 reg (odata, unchanged)
0 0 0 1 1 1 0 reg (odata, unchanged)
- 0 0 1 0 0 0 1 process(
i_data
)
- 0 0 1 1 0 0 1 process(
i_data
)
+ 0 0 1 0 0 0 1 process(
data_i
)
+ 0 0 1 1 0 0 1 process(
data_i
)
------- - - -
------- - - -
- 0 1 0 0 0 0 1 process(
i_data
)
+ 0 1 0 0 0 0 1 process(
data_i
)
0 1 0 1 1 1 0 reg (odata, unchanged)
0 1 0 1 1 1 0 reg (odata, unchanged)
- 0 1 1 0 0 0 1 process(
i_data
)
- 0 1 1 1 0 0 1 process(
i_data
)
+ 0 1 1 0 0 0 1 process(
data_i
)
+ 0 1 1 1 0 0 1 process(
data_i
)
------- - - -
------- - - -
- 1 0 0 0 0 1 1 process(
i_data
)
+ 1 0 0 0 0 1 1 process(
data_i
)
1 0 0 1 1 1 0 reg (odata, unchanged)
1 0 0 1 1 1 0 reg (odata, unchanged)
- 1 0 1 0 0 1 1 process(
i_data
)
- 1 0 1 1 0 1 1 process(
i_data
)
+ 1 0 1 0 0 1 1 process(
data_i
)
+ 1 0 1 1 0 1 1 process(
data_i
)
------- - - -
------- - - -
- 1 1 0 0 0 1 1 process(
i_data
)
+ 1 1 0 0 0 1 1 process(
data_i
)
1 1 0 1 1 1 0 reg (odata, unchanged)
1 1 0 1 1 1 0 reg (odata, unchanged)
- 1 1 1 0 0 1 1 process(
i_data
)
- 1 1 1 1 0 1 1 process(
i_data
)
+ 1 1 1 0 0 1 1 process(
data_i
)
+ 1 1 1 1 0 1 1 process(
data_i
)
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
------- - - -
Note: PoR is *NOT* involved in the above decision-making.
@@
-1127,10
+1127,10
@@
class UnbufferedPipeline2(ControlBase):
m.d.comb += self.p._ready_o.eq(~buf_full)
m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
m.d.comb += self.p._ready_o.eq(~buf_full)
m.d.sync += buf_full.eq(~self.n.ready_i_test & self.n.valid_o)
-
o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data
))
-
o_data = self._postprocess(o_data
)
- m.d.comb += eq(self.n.
o_data, o_data
)
- m.d.sync += eq(buf, self.n.
o_data
)
+
data_o = Mux(buf_full, buf, self.stage.process(self.p.data_i
))
+
data_o = self._postprocess(data_o
)
+ m.d.comb += eq(self.n.
data_o, data_o
)
+ m.d.sync += eq(buf, self.n.
data_o
)
return self.m
return self.m
@@
-1193,17
+1193,17
@@
class PassThroughHandshake(ControlBase):
m.d.comb += self.p.ready_o.eq(~self.n.valid_o | self.n.ready_i_test)
m.d.sync += self.n.valid_o.eq(p_valid_i | ~self.p.ready_o)
m.d.comb += self.p.ready_o.eq(~self.n.valid_o | self.n.ready_i_test)
m.d.sync += self.n.valid_o.eq(p_valid_i | ~self.p.ready_o)
- odata = Mux(pvr, self.stage.process(self.p.
i_data
), r_data)
+ odata = Mux(pvr, self.stage.process(self.p.
data_i
), r_data)
m.d.sync += eq(r_data, odata)
r_data = self._postprocess(r_data)
m.d.sync += eq(r_data, odata)
r_data = self._postprocess(r_data)
- m.d.comb += eq(self.n.
o_data
, r_data)
+ m.d.comb += eq(self.n.
data_o
, r_data)
return m
class RegisterPipeline(UnbufferedPipeline):
""" A pipeline stage that delays by one clock cycle, creating a
return m
class RegisterPipeline(UnbufferedPipeline):
""" A pipeline stage that delays by one clock cycle, creating a
- sync'd latch out of
o_data
and valid_o as an indirect byproduct
+ sync'd latch out of
data_o
and valid_o as an indirect byproduct
of using PassThroughStage
"""
def __init__(self, iospecfn):
of using PassThroughStage
"""
def __init__(self, iospecfn):
@@
-1214,7
+1214,7
@@
class FIFOControl(ControlBase):
""" FIFO Control. Uses SyncFIFO to store data, coincidentally
happens to have same valid/ready signalling as Stage API.
""" FIFO Control. Uses SyncFIFO to store data, coincidentally
happens to have same valid/ready signalling as Stage API.
- i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
+ data_i -> fifo.din -> FIFO -> fifo.dout -> data_o
"""
def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
"""
def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
@@
-1229,13
+1229,13
@@
class FIFOControl(ControlBase):
NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
(fwft=True, buffered=False)
NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
(fwft=True, buffered=False)
- NOTE 2:
i_data
*must* have a shape function. it can therefore
+ NOTE 2:
data_i
*must* have a shape function. it can therefore
be a Signal, or a Record, or a RecordObject.
data is processed (and located) as follows:
self.p self.stage temp fn temp fn temp fp self.n
be a Signal, or a Record, or a RecordObject.
data is processed (and located) as follows:
self.p self.stage temp fn temp fn temp fp self.n
-
i_data->process()->result->cat->din.FIFO.dout->cat(o_data
)
+
data_i->process()->result->cat->din.FIFO.dout->cat(data_o
)
yes, really: cat produces a Cat() which can be assigned to.
this is how the FIFO gets de-catted without needing a de-cat
yes, really: cat produces a Cat() which can be assigned to.
this is how the FIFO gets de-catted without needing a de-cat
@@
-1254,8
+1254,8
@@
class FIFOControl(ControlBase):
def elaborate(self, platform):
self.m = m = ControlBase.elaborate(self, platform)
def elaborate(self, platform):
self.m = m = ControlBase.elaborate(self, platform)
- # make a FIFO with a signal of equal width to the
o_data
.
- (fwidth, _) = shape(self.n.
o_data
)
+ # make a FIFO with a signal of equal width to the
data_o
.
+ (fwidth, _) = shape(self.n.
data_o
)
if self.buffered:
fifo = SyncFIFOBuffered(fwidth, self.fdepth)
else:
if self.buffered:
fifo = SyncFIFOBuffered(fwidth, self.fdepth)
else:
@@
-1264,9
+1264,9
@@
class FIFOControl(ControlBase):
# store result of processing in combinatorial temporary
result = _spec(self.stage.ospec, "r_temp")
# store result of processing in combinatorial temporary
result = _spec(self.stage.ospec, "r_temp")
- m.d.comb += eq(result, self.stage.process(self.p.
i_data
))
+ m.d.comb += eq(result, self.stage.process(self.p.
data_i
))
- # connect previous rdy/valid/data - do cat on
i_data
+ # connect previous rdy/valid/data - do cat on
data_i
# NOTE: cannot do the PrevControl-looking trick because
# of need to process the data. shaaaame....
m.d.comb += [fifo.we.eq(self.p.valid_i_test),
# NOTE: cannot do the PrevControl-looking trick because
# of need to process the data. shaaaame....
m.d.comb += [fifo.we.eq(self.p.valid_i_test),
@@
-1274,7
+1274,7
@@
class FIFOControl(ControlBase):
eq(fifo.din, cat(result)),
]
eq(fifo.din, cat(result)),
]
- # connect next rdy/valid/data - do cat on
o_data
+ # connect next rdy/valid/data - do cat on
data_o
connections = [self.n.valid_o.eq(fifo.readable),
fifo.re.eq(self.n.ready_i_test),
]
connections = [self.n.valid_o.eq(fifo.readable),
fifo.re.eq(self.n.ready_i_test),
]
@@
-1282,9
+1282,9
@@
class FIFOControl(ControlBase):
m.d.comb += connections
else:
m.d.sync += connections # unbuffered fwft mode needs sync
m.d.comb += connections
else:
m.d.sync += connections # unbuffered fwft mode needs sync
-
o_data = cat(self.n.o_data
).eq(fifo.dout)
-
o_data = self._postprocess(o_data
)
- m.d.comb +=
o_data
+
data_o = cat(self.n.data_o
).eq(fifo.dout)
+
data_o = self._postprocess(data_o
)
+ m.d.comb +=
data_o
return m
return m
diff --git
a/src/add/test_buf_pipe.py
b/src/add/test_buf_pipe.py
index 39d1f45f96af3ef2e1ac7a902755900d475fe0e0..48d5ac5228888256456b9fdddee27f5f1a1d260c 100644
(file)
--- a/
src/add/test_buf_pipe.py
+++ b/
src/add/test_buf_pipe.py
@@
-53,24
+53,24
@@
def tbench(dut):
yield
#yield dut.i_p_rst.eq(0)
yield dut.n.ready_i.eq(1)
yield
#yield dut.i_p_rst.eq(0)
yield dut.n.ready_i.eq(1)
- yield dut.p.
i_data
.eq(5)
+ yield dut.p.
data_i
.eq(5)
yield dut.p.valid_i.eq(1)
yield
yield dut.p.valid_i.eq(1)
yield
- yield dut.p.
i_data
.eq(7)
+ yield dut.p.
data_i
.eq(7)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.p.
i_data
.eq(2)
+ yield dut.p.
data_i
.eq(2)
yield
yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
yield
yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.
i_data
.eq(9)
+ yield dut.p.
data_i
.eq(9)
yield
yield dut.p.valid_i.eq(0)
yield
yield dut.p.valid_i.eq(0)
- yield dut.p.
i_data
.eq(12)
+ yield dut.p.
data_i
.eq(12)
yield
yield
- yield dut.p.
i_data
.eq(32)
+ yield dut.p.
data_i
.eq(32)
yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@
-89,25
+89,25
@@
def tbench2(dut):
yield
#yield dut.p.i_rst.eq(0)
yield dut.n.ready_i.eq(1)
yield
#yield dut.p.i_rst.eq(0)
yield dut.n.ready_i.eq(1)
- yield dut.p.
i_data
.eq(5)
+ yield dut.p.
data_i
.eq(5)
yield dut.p.valid_i.eq(1)
yield
yield dut.p.valid_i.eq(1)
yield
- yield dut.p.
i_data
.eq(7)
+ yield dut.p.
data_i
.eq(7)
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
- yield dut.p.
i_data
.eq(2)
+ yield dut.p.
data_i
.eq(2)
yield
yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
yield
yield from check_o_n_valid2(dut, 1) # ok *now* i_p_valid effect is felt
yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.
i_data
.eq(9)
+ yield dut.p.
data_i
.eq(9)
yield
yield dut.p.valid_i.eq(0)
yield
yield dut.p.valid_i.eq(0)
- yield dut.p.
i_data
.eq(12)
+ yield dut.p.
data_i
.eq(12)
yield
yield
- yield dut.p.
i_data
.eq(32)
+ yield dut.p.
data_i
.eq(32)
yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid2(dut, 1) # buffer still needs to output
yield dut.n.ready_i.eq(1)
yield
yield from check_o_n_valid2(dut, 1) # buffer still needs to output
@@
-147,7
+147,7
@@
class Test3:
continue
if send and self.i != len(self.data):
yield self.dut.p.valid_i.eq(1)
continue
if send and self.i != len(self.data):
yield self.dut.p.valid_i.eq(1)
- yield self.dut.p.
i_data
.eq(self.data[self.i])
+ yield self.dut.p.
data_i
.eq(self.data[self.i])
self.i += 1
else:
yield self.dut.p.valid_i.eq(0)
self.i += 1
else:
yield self.dut.p.valid_i.eq(0)
@@
-164,16
+164,16
@@
class Test3:
i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
- o_data = yield self.dut.n.o_data
- self.resultfn(
o_data
, self.data[self.o], self.i, self.o)
+ data_o = yield self.dut.n.data_o
+ self.resultfn(
data_o
, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
break
self.o += 1
if self.o == len(self.data):
break
-def resultfn_3(
o_data
, expected, i, o):
- assert
o_data
== expected + 1, \
+def resultfn_3(
data_o
, expected, i, o):
+ assert
data_o
== expected + 1, \
"%d-%d data %x not match %x\n" \
"%d-%d data %x not match %x\n" \
- % (i, o,
o_data
, expected)
+ % (i, o,
data_o
, expected)
def data_placeholder():
data = []
def data_placeholder():
data = []
@@
-240,23
+240,23
@@
class Test5:
i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
i_n_ready = yield self.dut.n.ready_i_test
if not o_n_valid or not i_n_ready:
continue
- if isinstance(self.dut.n.
o_data
, Record):
-
o_data
= {}
- dod = self.dut.n.
o_data
+ if isinstance(self.dut.n.
data_o
, Record):
+
data_o
= {}
+ dod = self.dut.n.
data_o
for k, v in dod.fields.items():
for k, v in dod.fields.items():
-
o_data
[k] = yield v
+
data_o
[k] = yield v
else:
else:
- o_data = yield self.dut.n.o_data
- self.resultfn(
o_data
, self.data[self.o], self.i, self.o)
+ data_o = yield self.dut.n.data_o
+ self.resultfn(
data_o
, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
break
self.o += 1
if self.o == len(self.data):
break
-def resultfn_5(
o_data
, expected, i, o):
+def resultfn_5(
data_o
, expected, i, o):
res = expected[0] + expected[1]
res = expected[0] + expected[1]
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d data %x not match %s\n" \
"%d-%d data %x not match %s\n" \
- % (i, o,
o_data
, repr(expected))
+ % (i, o,
data_o
, repr(expected))
def tbench4(dut):
data = []
def tbench4(dut):
data = []
@@
-273,7
+273,7
@@
def tbench4(dut):
if o_p_ready:
if send and i != len(data):
yield dut.p.valid_i.eq(1)
if o_p_ready:
if send and i != len(data):
yield dut.p.valid_i.eq(1)
- yield dut.p.
i_data
.eq(data[i])
+ yield dut.p.
data_i
.eq(data[i])
i += 1
else:
yield dut.p.valid_i.eq(0)
i += 1
else:
yield dut.p.valid_i.eq(0)
@@
-281,9
+281,9
@@
def tbench4(dut):
o_n_valid = yield dut.n.valid_o
i_n_ready = yield dut.n.ready_i_test
if o_n_valid and i_n_ready:
o_n_valid = yield dut.n.valid_o
i_n_ready = yield dut.n.ready_i_test
if o_n_valid and i_n_ready:
- o_data = yield dut.n.o_data
- assert
o_data
== data[o] + 2, "%d-%d data %x not match %x\n" \
- % (i, o,
o_data
, data[o])
+ data_o = yield dut.n.data_o
+ assert
data_o
== data[o] + 2, "%d-%d data %x not match %x\n" \
+ % (i, o,
data_o
, data[o])
o += 1
if o == len(data):
break
o += 1
if o == len(data):
break
@@
-331,11
+331,11
@@
def data_chain2():
return data
return data
-def resultfn_9(
o_data
, expected, i, o):
+def resultfn_9(
data_o
, expected, i, o):
res = expected + 2
res = expected + 2
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d received data %x not match expected %x\n" \
"%d-%d received data %x not match expected %x\n" \
- % (i, o,
o_data
, res)
+ % (i, o,
data_o
, res)
######################################################################
######################################################################
@@
-422,11
+422,11
@@
class ExampleLTBufferedPipeDerived(BufferedHandshake):
BufferedHandshake.__init__(self, stage)
BufferedHandshake.__init__(self, stage)
-def resultfn_6(
o_data
, expected, i, o):
+def resultfn_6(
data_o
, expected, i, o):
res = 1 if expected[0] < expected[1] else 0
res = 1 if expected[0] < expected[1] else 0
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d data %x not match %s\n" \
"%d-%d data %x not match %s\n" \
- % (i, o,
o_data
, repr(expected))
+ % (i, o,
data_o
, repr(expected))
######################################################################
######################################################################
@@
-492,11
+492,11
@@
class ExampleAddRecordPipe(UnbufferedPipeline):
UnbufferedPipeline.__init__(self, stage)
UnbufferedPipeline.__init__(self, stage)
-def resultfn_7(
o_data
, expected, i, o):
+def resultfn_7(
data_o
, expected, i, o):
res = (expected['src1'] + 1, expected['src2'] + 1)
res = (expected['src1'] + 1, expected['src2'] + 1)
- assert
o_data['src1'] == res[0] and o_data
['src2'] == res[1], \
+ assert
data_o['src1'] == res[0] and data_o
['src2'] == res[1], \
"%d-%d data %s not match %s\n" \
"%d-%d data %s not match %s\n" \
- % (i, o, repr(
o_data
), repr(expected))
+ % (i, o, repr(
data_o
), repr(expected))
class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
@@
-508,12
+508,12
@@
class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline):
UnbufferedPipeline.__init__(self, stage)
UnbufferedPipeline.__init__(self, stage)
-def resultfn_test11(
o_data
, expected, i, o):
+def resultfn_test11(
data_o
, expected, i, o):
res1 = expected.src1 + 1
res2 = expected.src2 + 1
res1 = expected.src1 + 1
res2 = expected.src2 + 1
- assert
o_data['src1'] == res1 and o_data
['src2'] == res2, \
+ assert
data_o['src1'] == res1 and data_o
['src2'] == res2, \
"%d-%d data %s not match %s\n" \
"%d-%d data %s not match %s\n" \
- % (i, o, repr(
o_data
), repr(expected))
+ % (i, o, repr(
data_o
), repr(expected))
######################################################################
######################################################################
@@
-575,11
+575,11
@@
class TestInputAdd:
self.op2 = op2
self.op2 = op2
-def resultfn_8(
o_data
, expected, i, o):
+def resultfn_8(
data_o
, expected, i, o):
res = expected.op1 + expected.op2 # these are a TestInputAdd instance
res = expected.op1 + expected.op2 # these are a TestInputAdd instance
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d data %s res %x not match %s\n" \
"%d-%d data %s res %x not match %s\n" \
- % (i, o, repr(
o_data
), res, repr(expected))
+ % (i, o, repr(
data_o
), res, repr(expected))
def data_2op():
data = []
def data_2op():
data = []
@@
-652,11
+652,11
@@
def data_chain1():
return data
return data
-def resultfn_12(
o_data
, expected, i, o):
+def resultfn_12(
data_o
, expected, i, o):
res = expected + 1
res = expected + 1
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d data %x not match %x\n" \
"%d-%d data %x not match %x\n" \
- % (i, o,
o_data
, res)
+ % (i, o,
data_o
, res)
######################################################################
######################################################################
@@
-728,11
+728,11
@@
class PassThroughTest(PassThroughHandshake):
stage = PassThroughStage(self.iospecfn)
PassThroughHandshake.__init__(self, stage)
stage = PassThroughStage(self.iospecfn)
PassThroughHandshake.__init__(self, stage)
-def resultfn_identical(
o_data
, expected, i, o):
+def resultfn_identical(
data_o
, expected, i, o):
res = expected
res = expected
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d data %x not match %x\n" \
"%d-%d data %x not match %x\n" \
- % (i, o,
o_data
, res)
+ % (i, o,
data_o
, res)
######################################################################
######################################################################
@@
-1023,7
+1023,7
@@
if __name__ == '__main__':
run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe2.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe2.il", "w") as f:
f.write(vl)
@@
-1055,7
+1055,7
@@
if __name__ == '__main__':
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- list(dut.p.
i_data) + [dut.n.o_data
]
+ list(dut.p.
data_i) + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_ltcomb_pipe.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_ltcomb_pipe.il", "w") as f:
f.write(vl)
@@
-1066,8
+1066,8
@@
if __name__ == '__main__':
test = Test5(dut, resultfn_7, data=data)
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o,
test = Test5(dut, resultfn_7, data=data)
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o,
- dut.p.
i_data.src1, dut.p.i_data
.src2,
- dut.n.
o_data.src1, dut.n.o_data
.src2]
+ dut.p.
data_i.src1, dut.p.data_i
.src2,
+ dut.n.
data_o.src1, dut.n.data_o
.src2]
vl = rtlil.convert(dut, ports=ports)
with open("test_recordcomb_pipe.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_recordcomb_pipe.il", "w") as f:
f.write(vl)
@@
-1083,7
+1083,7
@@
if __name__ == '__main__':
dut = ExampleBufPipeChain2()
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
dut = ExampleBufPipeChain2()
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipechain2.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipechain2.il", "w") as f:
f.write(vl)
@@
-1115,7
+1115,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe12.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe12.il", "w") as f:
f.write(vl)
@@
-1127,7
+1127,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe13.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe13.il", "w") as f:
f.write(vl)
@@
-1139,7
+1139,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
@@
-1151,7
+1151,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf16.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf16.il", "w") as f:
f.write(vl)
@@
-1163,7
+1163,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe17.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe17.il", "w") as f:
f.write(vl)
@@
-1175,7
+1175,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_passthru18.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_passthru18.il", "w") as f:
f.write(vl)
@@
-1187,7
+1187,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass19.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass19.il", "w") as f:
f.write(vl)
@@
-1199,7
+1199,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifo20.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_fifo20.il", "w") as f:
f.write(vl)
@@
-1211,7
+1211,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifopass21.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_fifopass21.il", "w") as f:
f.write(vl)
@@
-1223,8
+1223,8
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data.op1, dut.p.i_data
.op2] + \
- [dut.n.
o_data
]
+ [dut.p.
data_i.op1, dut.p.data_i
.op2] + \
+ [dut.n.
data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord22.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord22.il", "w") as f:
f.write(vl)
@@
-1236,8
+1236,8
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data.op1, dut.p.i_data
.op2] + \
- [dut.n.
o_data
]
+ [dut.p.
data_i.op1, dut.p.data_i
.op2] + \
+ [dut.n.
data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord23.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord23.il", "w") as f:
f.write(vl)
@@
-1248,8
+1248,8
@@
if __name__ == '__main__':
test = Test5(dut, resultfn_8, data=data)
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
test = Test5(dut, resultfn_8, data=data)
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data.op1, dut.p.i_data
.op2] + \
- [dut.n.
o_data
]
+ [dut.p.
data_i.op1, dut.p.data_i
.op2] + \
+ [dut.n.
data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord24.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord24.il", "w") as f:
f.write(vl)
@@
-1262,7
+1262,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_add2pipe25.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_add2pipe25.il", "w") as f:
f.write(vl)
@@
-1274,7
+1274,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass997.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass997.il", "w") as f:
f.write(vl)
@@
-1286,7
+1286,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe14.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe14.il", "w") as f:
f.write(vl)
@@
-1298,7
+1298,7
@@
if __name__ == '__main__':
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
ports = [dut.p.valid_i, dut.n.ready_i,
dut.n.valid_o, dut.p.ready_o] + \
- [dut.p.
i_data] + [dut.n.o_data
]
+ [dut.p.
data_i] + [dut.n.data_o
]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf999.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf999.il", "w") as f:
f.write(vl)
diff --git
a/src/add/test_fpadd_pipe.py
b/src/add/test_fpadd_pipe.py
index 67a6f9ebabe1399ea980d35beb1495c39ab13913..df25e55fe7a2f63992ffad68f6cfbe47faa9bd1c 100644
(file)
--- a/
src/add/test_fpadd_pipe.py
+++ b/
src/add/test_fpadd_pipe.py
@@
-39,9
+39,9
@@
class InputTest:
op1, op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
op1, op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
- yield rs.
i_data
.a.eq(op1)
- yield rs.
i_data
.b.eq(op2)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
data_i
.a.eq(op1)
+ yield rs.
data_i
.b.eq(op2)
+ yield rs.
data_i
.mid.eq(mid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
@@
-89,8
+89,8
@@
class InputTest:
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- out_mid = yield n.
o_data
.mid
- out_z = yield n.
o_data
.z
+ out_mid = yield n.
data_o
.mid
+ out_z = yield n.
data_o
.z
out_i = 0
out_i = 0
diff --git
a/src/add/test_fsm_experiment.py
b/src/add/test_fsm_experiment.py
index 4d05bba86485f79d3e5d54d0e0030a890e4a69bc..5b5ececbc09931f1ba038f42dd3802d0b6c2cb3a 100644
(file)
--- a/
src/add/test_fsm_experiment.py
+++ b/
src/add/test_fsm_experiment.py
@@
-104,15
+104,15
@@
class FPDIVPipe(ControlBase):
m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
- m.d.comb += self.n.
o_data
.eq(self.fpdiv.out_z.v)
+ m.d.comb += self.n.
data_o
.eq(self.fpdiv.out_z.v)
return m
return m
-def resultfn(
o_data
, expected, i, o):
+def resultfn(
data_o
, expected, i, o):
res = expected + 1
res = expected + 1
- assert
o_data
== res, \
+ assert
data_o
== res, \
"%d-%d received data %x not match expected %x\n" \
"%d-%d received data %x not match expected %x\n" \
- % (i, o,
o_data
, res)
+ % (i, o,
data_o
, res)
if __name__ == "__main__":
if __name__ == "__main__":
diff --git
a/src/add/test_inout_mux_pipe.py
b/src/add/test_inout_mux_pipe.py
index a51ccf1ae0cbeb39e357516582569588df3d394c..35abe2eaf46b3aa148826b6821640cf39dfe2786 100644
(file)
--- a/
src/add/test_inout_mux_pipe.py
+++ b/
src/add/test_inout_mux_pipe.py
@@
-67,9
+67,9
@@
class InputTest:
op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.idx.eq(i)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.idx.eq(i)
+ yield rs.
data_i
.mid.eq(mid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
@@
-113,9
+113,9
@@
class InputTest:
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- out_mid = yield n.
o_data
.mid
- out_i = yield n.
o_data
.idx
- out_v = yield n.
o_data
.data
+ out_mid = yield n.
data_o
.mid
+ out_i = yield n.
data_o
.idx
+ out_v = yield n.
data_o
.data
print ("recv", out_mid, out_i, hex(out_v))
print ("recv", out_mid, out_i, hex(out_v))
@@
-158,8
+158,8
@@
class OutputTest:
mid = self.di[i][1]
rs = dut.p
yield rs.valid_i.eq(1)
mid = self.di[i][1]
rs = dut.p
yield rs.valid_i.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.mid.eq(mid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
diff --git
a/src/add/test_outmux_pipe.py
b/src/add/test_outmux_pipe.py
index bec958e51c1d90d7330e77638a77ccb9f8e46095..a633d92bebdc8e652dfcc02d99b48dc51ea4f457 100644
(file)
--- a/
src/add/test_outmux_pipe.py
+++ b/
src/add/test_outmux_pipe.py
@@
-66,8
+66,8
@@
class OutputTest:
mid = self.di[i][1]
rs = dut.p
yield rs.valid_i.eq(1)
mid = self.di[i][1]
rs = dut.p
yield rs.valid_i.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.mid.eq(mid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
@@
-98,7
+98,7
@@
class OutputTest:
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- out_v = yield n.
o_data
+ out_v = yield n.
data_o
print ("recv", mid, out_i, hex(out_v))
print ("recv", mid, out_i, hex(out_v))
@@
-140,11
+140,11
@@
class TestSyncToPriorityPipe(Elaboratable):
def ports(self):
res = [self.p.valid_i, self.p.ready_o] + \
def ports(self):
res = [self.p.valid_i, self.p.ready_o] + \
- self.p.
i_data
.ports()
+ self.p.
data_i
.ports()
for i in range(len(self.n)):
res += [self.n[i].ready_i, self.n[i].valid_o] + \
for i in range(len(self.n)):
res += [self.n[i].ready_i, self.n[i].valid_o] + \
- [self.n[i].
o_data
]
- #self.n[i].
o_data
.ports()
+ [self.n[i].
data_o
]
+ #self.n[i].
data_o
.ports()
return res
return res
diff --git
a/src/add/test_prioritymux_pipe.py
b/src/add/test_prioritymux_pipe.py
index 366986af455aebf0322a8770e456e4a3ebc055b6..5f7891e881271fad4ba5f730d8d9070c29e38024 100644
(file)
--- a/
src/add/test_prioritymux_pipe.py
+++ b/
src/add/test_prioritymux_pipe.py
@@
-132,9
+132,9
@@
class InputTest:
op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
op2 = self.di[mid][i]
rs = dut.p[mid]
yield rs.valid_i.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.idx.eq(i)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.idx.eq(i)
+ yield rs.
data_i
.mid.eq(mid)
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
yield
o_p_ready = yield rs.ready_o
while not o_p_ready:
@@
-174,9
+174,9
@@
class InputTest:
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- mid = yield n.
o_data
.mid
- out_i = yield n.
o_data
.idx
- out_v = yield n.
o_data
.data
+ mid = yield n.
data_o
.mid
+ out_i = yield n.
data_o
.idx
+ out_v = yield n.
data_o
.data
print ("recv", mid, out_i, hex(out_v))
print ("recv", mid, out_i, hex(out_v))